Balanced high-capacity switch
View Patent ↗A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.
1. A switch comprising:
a plurality of switch units arranged in a lattice structure of row arrays of switch units and column arrays of switch units wherein switch units of each said row array are interconnected to form a full row mesh and switch units of each said column array are interconnected to form a full column mesh;
a plurality of channels;
a plurality of balanced connectors each balanced connector connecting to a subset of said switch units having non-intersecting coordinates, where coordinates of each switch unit are derived from a row array and a column array to which said each switch unit belongs; and
wherein each balanced connector cyclically connects a subset of channels from among said plurality of channels exclusively to the subset of said switch units connected to said balanced connector during successive time intervals of a time frame.
2. The switch of claim 1 further including a plurality of edge nodes, each edge node having a channel to one of said balanced connectors and a channel from one of said switch units.
3. The switch of claim 1 wherein at least one of said switch units comprises a bufferless switch fabric.
4. The switch of claim 1 wherein said at least one of said switch units has an optical switch fabric.
5. The switch of claim 1 wherein said each balanced connector comprises a plurality of rotator units having graduated rotation shifts, so that the rotation shift of each rotator unit is larger than the rotation shift of a preceding rotator unit.
6. The switch of claim 1 wherein any two switch units in said subset of said switch units belong to different row arrays and different column arrays.
7. The switch of claim 1 further including a plurality of edge nodes each having a channel from one of said balanced connectors and a channel to one of said switch units.
8. The switch of claim 1 further comprising:
a plurality of array controllers each array controller associated with one of said row arrays and coupled to a slave controller of each switch unit in said one of said row arrays; and
a master controller coupled to each of said array controllers.
9. The switch of claim 8 wherein said array controllers are associated with a group of host switch units selected from among said plurality of switch units so that:
each host switch unit supports only one array controller; and
the host switch units have non-intersecting coordinates, where coordinates of any switch unit are derived from the row array and column array to which said any switch unit belongs.
10. The switch of claim 8 further comprising a scheduler associated with said master controller, said scheduler operable to:
receive connection requests each connection request specifying an incoming channel, an outgoing channel, and a specified number of time slots in a time-slotted frame; and
perform a vacancy-matching process to find a free path for each of said specified number of time slots for said each connection request.
11. The switch of claim 8 further comprising a time counter coupled to each of said array controllers, said time counter providing a reference time for time-locking external nodes to said plurality of switch units.
12. An asymmetrical switch comprising:
a plurality of input ports;
a plurality of output ports
a switching fabric for connecting each of said input ports to at least one of said output ports;
and
a plurality of balanced connectors each balanced connector for cyclically connecting a subset of ingress channels from among a plurality of ingress channels exclusively to a subset of input ports from among said plurality of input ports during successive time intervals of a time frame;
wherein said switching fabric comprises a plurality of switch units arranged in row arrays of switch units interconnected to form a full row mesh and column arrays of switch units interconnected to form a full column mesh; and
wherein said subset of input ports comprises one input port of each switch unit of a diagonal set of switch units, where any two switch units of a diagonal set of switch units belong to different rows and different columns.
13. The asymmetrical switch of claim 12 wherein said each a balanced connector equitably connects each ingress channel of said subset of ingress channels to each input port of said subset of input ports during said time frame.
14. The asymmetrical switch of claim 12 wherein said each balanced connector comprises a plurality of rotator units having graduated rotation shifts selected so that during said time frame, any combination of two ingress channels from among said plurality of ingress channels connects only once to input ports of a same switch unit of said diagonal set of switch units.
15. The switching system of claim 12 wherein said switching fabric comprises optical switch units interconnected in a second-order mesh structure so that each of said input ports has multiple paths to each of said output ports.
16. The switching system of claim 12 wherein said switch fabric is time-multiplexed over a repetitive time frame.
17. The switching system of claim 16 further comprising a master controller for selecting at least one path and at least one time slot in said repetitive time frame to transfer a signal from each said ingress channel to at least one of said output ports.