Calculating circuit and method for computing an

1. A signal processing method for generating an output signal Z out (j) representing an output number approximating an N-th root or a reciprocal of an input number represented by an input signal Z in , the method comprising the iterative steps:

in an apparatus that includes a subtractor circuit, integrator circuit and multiplier circuit:

(a) generating an error signal E(f) representing a difference between a first signal and a feedback signal at a j-th iteration,

(b) integrating said error signal E(j) for obtaining said output signal Z out (j);

(c) generating the feedback signal Z fb (j);

(d) repeating steps (i) to (iii) as required to obtain said N-th root or said reciprocal with a required accuracy.

2. The method of claim 1 wherein the step of integrating said error signal E(j) includes:

(One) multiplying said error signal E(j) by a gain factor K, and

(Two) computing said output signal representing said output number Z out (j) according to the equation Z out (j)=Z out (j−1)+K·E(j).

3. The method of claim 2 wherein the value of K being a function of the input signal level.

4. The method of claim 3 wherein the value of K is equal to 2/Z in .

5. The method of claim 3 wherein the value of K is less than 2/Z in .

6. The method of claim 2 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.

7. The method of claim 1 wherein said first signal is said input signal Z in .

8. The method of claim 1 wherein said first signal is a reference signal.

9. The method of claim 1 further including generating the input signal Z in by squaring a received signal to generate an intermediate signal and then lowpass filtering the intermediate signal, wherein the output signal Z out (j) corresponds to an amount of energy in the received signal.

10. The method of claim 1 wherein said feedback signal Z fb is said output signal Z out (j) raised to the power N.

11. The method of claim 1 wherein said feedback signal Z fb (j) is a product of said output signal Z out (j) and said input signal Z in .

12. A signal processing method for generating an output signal Z out (j) representing an output number approximating an N-th root of an input number represented by an input signal Z in , the method comprising the iterative steps:

in an apparatus that includes a subtractor circuit, integrator circuit and multiplier circuit:

(a) generating an error signal E(j) at a j-th iteration representing a difference between said input signal Z in , and a feedback signal Z fb (j) representing said output signal raised to the power N,

(b) integrating said error signal E(j) for obtaining said output signal Z out (j);

(c) generating said feedback signal;

(d) repeating steps (i) to (iii) as required to obtain said N-th root with a required accuracy.

13. The method of claim 12 wherein the step of integrating said error signal E(j) includes:

(One) multiplying said error signal E(j) by a gain factor K,

(Two) computing said output signal representing said output number Z out (j) according to the equation Z out (j)=Z out (j−1)+KE(j).

14. The method of claim 13 wherein the value of K being a function of the input signal level.

15. The method of claim 14 wherein the value of K is equal to 2/Z in .

16. The method of claim 14 wherein the value of K is less than 2/Z in .

17. The method of claim 13 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.

18. The method of claim 12 , further including generating the input signal Z in by squaring a received signal to generate an intermediate signal and then lowpass filtering the intermediate signal, wherein the output signal Z out (j) corresponds to an amount of energy in the received signal.

19. A signal processing method for generating an output signal Z out (j) representing an output number approximating a reciprocal of an input number represented by an input signal Z in , the method comprising the iterative steps:

in an apparatus that includes a subtractor circuit, integrator circuit and multiplier circuit:

(a) generating an error signal E(j) representing a difference between a reference signal and a feedback signal Z fb (j) at a j-th iteration,

(b) integrating said error signal E(j) for obtaining said output signal Z out (j); (c) generating said feedback signal representing a product of said output signal Z out (j) and said input signal Z in ;

(c) repeating steps (i) to (iii) as required to obtain said reciprocal of the input number with a required accuracy.

20. The method of claim 19 wherein the step of integrating said error signal E(j) includes:

(One) multiplying said error signal E(j) by a gain factor K,

(Two) computing said output signal representing said output number Z out (j) according to the equation Z out (j)=Z out (j−1)+K·E(j).

21. The method of claim 20 wherein said gain factor K is limited to the values between 0 and ½.

22. The method of claim 20 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.

23. The method of claim 19 wherein said reference signal is represented by a constant value equal to 1.