Top-gate thin-film transistor
View Patent ↗A thin-film transistor, such as a top-gate thin-film transistor, is provided herein. The thin-film transistor has a performance-enhancing layer, such as a performance-enhancing bottom layer, comprising a polymer other than a polyimide. In specific embodiments, the polymer is selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. In other embodiments, it is a self-assembling polymeric monolayer of a silane agent and an organophosphonic acid. The performance-enhancing layer directly contacts the substrate. The layer improves the carrier mobility and current on/off ratio of the thin film transistor.
1. A top-gate thin film transistor comprising, in sequence:
a substrate having functional groups on its surface;
a performance-enhancing bottom layer;
a semiconductor layer; and
a dielectric layer;
wherein the performance-enhancing bottom layer is positioned between the substrate and the semiconductor layer; and,
wherein the performance-enhancing bottom layer is a self-assembling monolayer formed from a precursor having the following formula:
X—Y
wherein X is a group that is reactive with the functional groups on the substrate surface, and Y is a linear or branched hydrocarbon or heteroatom-containing group having 1 to about 60 carbon atoms or from 1 to about 30 carbon atoms; and
wherein X is selected from the groups consisting of —PO 3 H 3 , —SiCl 3 , —SiCl(CH 3 ) 2 , and —SiCl 2 CH 3 .
2. The thin film transistor of claim 1 , wherein the precursor is 1-phosphonohexadecane.
3. The thin film transistor of claim 1 , wherein the performance-enhancing bottom layer has a thickness of from about 0.5 nanometers to about 5 nanometers.
4. The thin film transistor of claim 1 , wherein the semiconductor layer comprises a polythiophene.
5. The thin film transistor of claim 1 , wherein the performance-enhancing bottom layer has a surface roughness of less than about 10 nanometers.
6. The thin film transistor of claim 1 , wherein the performance-enhancing bottom layer has a surface water contact angle greater than about 80 degrees.
7. The thin film transistor of claim 5 , wherein the performance-enhancing bottom layer has a surface roughness of less than about 5 nanometers.