Gate driver for a display device and method of driving the same
View Patent ↗A gate driver for a display device includes a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and a dummy clock provided to the plurality of shift registers during a vertical blank time to reduce a stress voltage in the shift registers, wherein an output of each of the shift registers is reset to a low state power supply voltage by an output signal of the next shift register.
1. A gate driver for a display device, comprising:
a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and
a dummy clock provided to the plurality of shift registers during a vertical blank time to reduce a stress voltage in the shift registers,
wherein the dummy clock is simultaneously applied to all shift registers during the vertical blank time.
2. The gate driver according to claim 1 , wherein the multi-phase clocks include two-phase clocks generated in synchronization with horizontal periods.
3. The gate driver according to claim 1 , wherein the multi-phase clocks further includes clocks having three or more phases and having pulses that partially overlap with one another.
4. The gate driver according to claim 1 , wherein each of the shift registers includes a first transistor that is switched on or off by the dummy clock.
5. The gate driver according to claim 4 , wherein each of the shift registers includes a second transistor having a gate connected to the first transistor, and the stress voltage in the second transistor is reduced by applying a low state power supply voltage to the gate of the second transistor by turning on the first transistor with the dummy clock.
6. The gate driver according to claim 4 , wherein each of the shift registers includes a second transistor having a gate connected to the first transistor, and the stress voltage in the second transistor is reduced by applying a voltage level lower than a low state power supply voltage by turning on the first transistor with the dummy clock.
7. The gate driver according to claim 1 , wherein the dummy clock has a high-state pulse during the vertical blank time.
8. The gate driver according to claim 7 , wherein the width of the high-state pulse is identical to the vertical blank time.
9. The gate driver according to claim 7 , wherein the width of the high-state pulse is smaller than the vertical blank time.
10. The gate driver according to claim 1 , wherein an output of each of the shift registers is reset to a low state power supply voltage by an output signal of the next shift register.
11. A method of driving a gate driver for a display device including a plurality of shift registers, the method comprising:
applying multi-phase clocks to the plurality of shift registers to sequentially generate output signals during a single frame period; and
applying a dummy clock to the shift resisters to reduce a stress voltage in the shift registers during a vertical blank time,
wherein the dummy clock is simultaneously applied to all shift registers during the vertical blank time.
12. The method according to claim 11 , further comprising:
resetting an output of each of the shift registers to a low state power supply voltage by applying an output signal of the next shift register.
13. The method according to claim 11 , wherein the stress voltage is reduced by a low state power supply voltage.
14. The method according to claim 11 , wherein the stress voltage is reduced by a voltage level lower than the low state power supply voltage.
15. The method according to claim 11 , wherein the dummy clock has a high-state pulse during the vertical blank time.
16. The method according to claim 15 , wherein the width of the high-state pulse is identical to the vertical blank time.
17. The method according to claim 15 , wherein the width of the high-state pulse is smaller than the vertical blank time.