Methods and apparatus for producing an IC identification number

1. A method comprising:

testing a static random access memory (SRAM) to: (i) identify at least some memory cells of the SRAM that have an access speed margin at least one of lower than a predetermined threshold and higher than a predetermined threshold; or (ii) identify at least some memory cells of the SRAM that have an access time at least one of greater than a predetermined threshold and lower than a predetermined threshold;

using addresses of at least some of the identified memory cells of the SRAM as at least a basis of a identification number; and

storing the identification number in memory for subsequent retrieval.

2. The method of claim 1 , wherein the identification number is substantially unique and substantially repeatable.

3. The method of claim 1 , further comprising processing the addresses of at least some of the memory cells of the SRAM to form the identification number.

4. The method of claim 1 , further comprising:

storing the identification number with an administrative entity;

re-testing for a subsequent identification number using the testing step; and

transmitting the subsequent identification number to the administrative entity for verification.

5. A method, comprising:

setting a supply voltage of a static random access memory (SRAM) below its normal operating voltage;

identifying at least some memory cells of the SRAM that fail a read and/or write test;

using addresses of at least some of an identified memory cells of the SRAM at least as a basis of the identification number; and

storing the identification number in memory for subsequent retrieval.

6. The method of claim 5 , further comprising:

repeating the setting steps at at least one lower or higher level of the supply voltage to identifying at least some further memory cells of the SRAM that fail a read and/or write test; and

using addresses of at least some of the further identified memory cells of the SRAM as at least part of the identification number.

7. The method of claim 5 , further comprising processing the addresses of at least some of the memory cells of the SRAM to form the identification number.

8. A method, comprising:

testing a static random access memory (SRAM) by at least one of: (i) identifying at least some memory cells of the SRAM that have an access speed margin at least one of lower than a predetermined threshold and higher than a predetermined threshold or identifying at least some memory cells of the SRAM that have an access time at least one of higher than a predetermined threshold and lower than a predetermined threshold, and (ii) setting a supply voltage to the SRAM to its normal operating voltage and identifying at least some memory cells of the SRAM that fail a read and/or write test;

repairing at least some of the memory cells resulting in failure of the testing step;

using repair addresses of at least some of the repaired memory cells of the SRAM at least as a basis of an identification number; and

storing the identification number in memory for subsequent retrieval.

9. The method of claim 8 , further comprising processing the addresses of at least some of the memory cells of the SRAM to form the identification number.

10. A method, comprising:

testing a static random access memory (SRAM) to obtain performance data on the SRAM;

using the performance data of the SRAM as at least a basis of a identification number;

storing the identification number in memory for subsequent retrieval;

producing a sum of products on at least some digits of the identification number and a subsequent identification number; and

verifying the subsequent identification number when the sum of products exceeds a predetermined threshold.

11. The method of claim 10 , further comprising:

storing the identification number with an administrative entity;

re-testing for a subsequent identification number using the testing step; and

transmitting the subsequent identification number to the administrative entity for verification.

12. An apparatus, comprising:

a static random access memory (SRAM); and

an interrogation circuit operable to: (i) obtain performance data on the SRAM, (ii) identify at least some memory cells of the SRAM that have an access speed margin at least one of lower than a predetermined threshold and higher than a predetermined threshold in order to obtain the performance data or identify at least some memory cells of the SRAM that have an access time at least one of higher than a predetermined threshold and lower than a predetermined threshold in order to obtain the performance data, and (iii) use addresses of at least some of the memory cells of the SRAM at least as a basis of an identification number.

13. The apparatus of claim 12 , wherein the identification number is substantially unique and substantially repeatable.

14. The apparatus of claim 12 , wherein the interrogation circuit is further operable to:

power up the SRAM;

interrogate a statistically large number of memory cells of the SRAM;

use contents of at least some of the memory cells as at least the basis of the identification number.

15. An apparatus, comprising:

a static random access memory (SRAM); and

an interrogation circuit operable to set a supply voltage to the SRAM below its normal operating voltage; identify at least some memory cells of the SRAM that fail a read and/or write test in order to produce the performance data; and use addresses of at least some of the memory cells of the SRAM at least as a basis of an identification number.

16. The apparatus of claim 15 , wherein the interrogation circuit is further operable to:

repeat setting and identifying functions at at least one lower or higher level of the supply voltage to obtain further performance data; and

use addresses of at least some further identified memory cells of the SRAM as at least part of the identification number.

17. An apparatus, comprising:

a static random access memory (SRAM); and

an interrogation circuit operable to use repair addresses as at least a basis of an identification number, the repair addresses being obtained by at least one of: (i) identifying at least some memory cells of the SRAM that have an access speed margin lower than a predetermined threshold or identifying at least some memory cells of the SRAM that have an access time greater than a predetermined threshold; (ii) setting a supply voltage to the SRAM to its normal operating voltage and identifying at least some memory cells of the SRAM that fail a read and/or write test; and (iii) repairing at least some of the memory cells resulting in failure.