Methods and apparatus for random number generation
View Patent ↗Methods and apparatus provide for powering up a static random access memory (SRAM); interrogating at least some contents of the SRAM resulting from power up; and using the contents as at least a basis of a random number.
1. A method, comprising:
powering up a static random access memory (SRAM);
interrogating at least some contents of the SRAM resulting from power up;
reading predetermined storage locations of the SRAM to obtain the contents of the SRAM; and
using the contents as at least a basis of a random number.
2. The method of claim 1 , further comprising post processing the contents of the SRAM to produce the random number.
3. The method of claim 2 , wherein the contents of the SRAM is of N bits and the random number is of M bits, where N>M.
4. The method of claim 2 , wherein the post processing includes using a hash algorithm to produce the random number.
5. The method of claim 2 , wherein the post processing includes creating an M-bit message digest from the contents of the SRAM.
6. The method of claim 5 , wherein the message digest is produced using one of MD5, MD4 and MD2 algorithms.
7. The method of claim 2 , further comprising using a portion of the SRAM to store program code for executing the post processing to produce the random number.
8. An apparatus, comprising:
a static random access memory (SRAM) including a plurality of storage locations operable to latch into a logic high or a logic low upon power up; and
an interrogation circuit operable to obtain contents of at least some of the storage locations, and including a built in test circuit operable to read predetermined storage locations of the SRAM to obtain the contents of the SRAM, where the contents are usable as at least a basis for a random number.
9. The apparatus of claim 8 , wherein the built in test circuit includes an address generator and a controller operable to produce addresses of the predetermined storage locations.
10. The apparatus of claim 8 , wherein the interrogation circuit includes:
a processor operable to execute program code that causes the processor to read at least some storage locations of the SRAM to obtain the contents of the SRAM; and
a storage circuit coupled to the processor and operable to store the program code.
11. The apparatus of claim 10 , wherein the processor is operable to post process the contents of the SRAM to produce the random number by executing further program code.
12. The apparatus of claim 11 , wherein at least one of:
the further program code is operable to cause the processor to carry out a hash algorithm to produce the random number;
the further program code is operable to cause the processor to carry out an M-bit message digest from the contents of the SRAM; and
the further program code is operable to cause the processor to carry out at least one of MD5, MD4 and MD2 algorithms.
13. The apparatus of claim 11 , wherein the processor is operable to read the further program code from the storage circuit into a portion of the SRAM for executing the post processing to produce the random number.
14. The apparatus of claim 11 , wherein the storage circuit is disposed on-chip with the processor.
15. The apparatus of claim 8 , further comprising a post processing circuit operable to manipulate the contents of the SRAM to produce the random number.
16. The apparatus of claim 15 , wherein the post processing circuit is operable to carry out a hash algorithm to produce the random number.
17. The apparatus of claim 15 , wherein at least one of:
the post processing circuit is operable to create an M-bit message digest from the contents of the SRAM; and
the message digest is produced using one of MD5, MD4and MD2algorithms.
18. An apparatus, comprising:
a plurality of processors capable of operative communication with a main memory;
a respective local static random access memory (SRAM) coupled to each of the processors, each local SRAM including a plurality of storage locations operable to latch into a logic high or a logic low upon power up; and
a respective interrogation circuit operable to obtain contents of at least some of the storage locations of an associated local SRAM, and including a built in test circuit operable to read predetermined storage locations of the SRAM to obtain the contents of the SRAM, where the contents are usable as at least a basis for a random number.