Methods and apparatus for reducing power consumption in a processor using clock signal control
View Patent ↗Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
1. An apparatus, comprising:
a clock control unit operable to produce a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode;
at least one divider/gate circuit operable to produce a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; and
at least one local clock buffer circuit operable to produce a local clock signal from a system clock signal as a function of the gate signal,
wherein at least one signal propagation latch circuit is interposed between the clock control unit and the divider/gate circuit.
2. The apparatus of claim 1 , wherein a plurality of signal propagation latch circuits are interposed between the clock control unit and the divider/gate circuit.
3. The apparatus of claim 2 , wherein there are no signal propagation latch circuits interposed between the divider/gate circuit and the local clock buffer circuit.
4. The apparatus of claim 2 , further comprising at least one signal propagation latch circuit interposed between the divider/gate circuit and the local clock buffer circuit.
5. The apparatus of claim 4 , wherein a greater number of signal propagation latch circuits are interposed between the control signal and the divider/gate circuit than between the divider/gate circuit and the local clock buffer circuit.
6. The apparatus of claim 1 , wherein the divider/gate circuit is operable to produce the gate signal such that the oscillation at a local clock frequency is lower than a frequency of the system clock.
7. The apparatus of claim 6 , wherein the divider/gate circuit includes a gated digital oscillator operable to use the control signal to enable the digital oscillator to produce the gate signal.
8. The apparatus of claim 6 , wherein the local clock buffer circuit is operable to produce the local clock signal from the system clock signal such that a frequency of the local clock signal is synchronized with the local clock frequency of the gate signal.
9. The apparatus of claim 8 , wherein the local clock buffer circuit includes combinational logic to produce the local clock signal from the system clock signal as a function of the gate signal.
10. The apparatus of claim 9 , wherein the local clock buffer circuit includes at least one of an AND gate and a NAND gate receiving the system clock signal and the gate signal and producing the local clock signal therefrom.
11. A method, comprising:
producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode;
producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level;
producing a local clock signal from a system clock signal as a function of the gate signal; and
interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
12. The method of claim 11 , further comprising interposing a plurality of signal propagation latch circuits between the origin of the control signal and the location at which the gate signal is produced.
13. The method of claim 12 , further comprising interposing no signal propagation latch circuits between the location at which the gate signal is produced and the location at which the local clock signal is produced.
14. The method of claim 12 , further comprising interposing at least one signal propagation latch circuit between the location at which the gate signal is produced and the location at which the local clock signal is produced.
15. The method of claim 14 , further comprising interposing a greater number of signal propagation latch circuits between the origin of the control signal and the location at which the gate signal is produced than between the location at which the gate signal is produced and the location at which the local clock signal is produced.
16. The method of claim 10 , further comprising producing the gate signal such that the oscillation at a local clock frequency is lower than a frequency of the system clock.
17. The method of claim 16 , further comprising producing the local clock signal from the system clock signal such that a frequency of the local clock signal is synchronized with the local clock frequency of the gate signal.