Data-directed frequency-and-phase lock loop
View Patent ↗A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
1. A frequency acquisition and phase-lock loop having a symbol rate, comprising:
a voltage controller oscillator that provides an I output and Q output;
a first multiplier that receives the first input and the I and Q outputs, and provides I′ and Q′ outputs;
a second multiplier that multiplies the I′ and Q′ outputs by a first fixed frequency to produce I″ and Q″ outputs;
a third multiplier that receives the I″ and Q″ outputs and convolves them to produce I′″ and Q′″ outputs;
a fourth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a second fixed frequency to produce first I″″ and Q″″ outputs;
a fifth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a third fixed frequency to produce second I″″ and Q″″ outputs;
first and second low-pass filters that receive the first and second I″″ outputs respectively, to produce first and second filtered I″″ outputs, respectively;
a sixth and seventh multipliers that receive the first and second Q″″ outputs, respectively, and the first and second filtered I″″ outputs, respectively, to produce first and second response outputs, respectively;
a summer that receives the first and second response outputs to produce a combined response signal;
a third low-pass filter that receives the combined response signal to produce a filtered combined response signal;
wherein the filtered combined response signal is fed back to the voltage controlled oscillator.
2. The frequency acquisition and phase-lock loop of claim 1 , wherein the first fixed frequency is ¼ of the symbol rate.
3. The frequency acquisition and phase-lock loop of claim 1 , wherein the second and third fixed frequencies differ by ½ of the symbol frequency.
4. The frequency acquisition and phase-lock loop of claim 3 , wherein the second fixed frequency is ¼ of the symbol rate.
5. The frequency acquisition and phase-lock loop of claim 1 , wherein the combined response signal is amplified before it is filtered.
6. The frequency acquisition and phase-lock loop of claim 1 , wherein the filtered combined response signal is amplified before it is returned to the voltage controller oscillator.
7. A frequency acquisition and phase-lock loop having a symbol rate and comprising:
a voltage controlled oscillator that provides an I output and a Q outputs;
a first multiplier that receives the first input and the I and Q outputs, and provides I′ and Q′ outputs;
a second multiplier that multiplies the I′ and Q′ outputs by ¼ the symbol rate to produce I″ and Q″ outputs;
a third multiplier that receives the I″ and Q″ outputs and convolves them to produce I′″ and Q′″ outputs;
a fourth multiplier that receives the I′″ and Q′″ outputs and multiplies them by ¼ of the symbol rate to produce first I″″ and Q″″ outputs;
a fifth multiplier that receives the I′″ and Q′″ outputs and multiplies them by ¾ of the symbol rate to produce second I″″ and Q″″ outputs;
first and second low-pass filters that receive the first and second I″″ outputs respectively to produce first and second filtered I″″ outputs, respectively;
a sixth and seventh multiplier that receives the first and second Q″″ outputs, respectively, and the first and second filtered I″″ outputs, respectively, to produce first and second response outputs, respectively;
a summer that receives the first and second response outputs to produce a combined response signal;
a third low-pass filter that receives the combined response signal and provides a filtered combined response signal;
an amplifier that receives the filtered combined response signal to produce an amplified filtered combined response signal that is fed back to the voltage controlled oscillator.
8. A symbol clock recovery loop for a symbol clock having a symbol clock control, the symbol clock recovery loop having a symbol rate and comprising:
a voltage controlled oscillator having an I output and a Q output;
a first multiplier that receives the first input and the I and Q outputs, and provides I′ and Q′ outputs;
a second multiplier that multiplies the I′ and Q′ outputs by a first fixed frequency to produce I″ and Q″ outputs;
a third multiplier that receives the I″ and Q″ outputs and convolves them to produce I′″ and Q′″ outputs;
a fourth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a second fixed frequency to produce first I″″ and Q″″ outputs;
a fifth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a third fixed frequency to produce second I″″ and Q″″ outputs;
first and second low-pass filters that receive the first and second I″″ outputs respectively to produce first and second filtered I″″ outputs, respectively;
a sixth and seventh multiplier that receives the first and second Q″″ outputs, respectively, and the first and second filtered I″″ outputs, respectively, to produce first and second response outputs, respectively;
a difference summer that receives the first and second response outputs to produce a difference response signal; and
a third low-pass filter that receives the difference response signal to produce a filtered difference response signal.
9. The frequency acquisition and phase-lock loop of claim 8 , wherein the first fixed frequency is ¼ of the symbol rate.
10. The frequency acquisition and phase-lock loop of claim 8 , wherein the second and third fixed frequencies differ by ½ of the symbol frequency.
11. The frequency acquisition and phase-lock loop of claim 10 , wherein the second fixed frequency is ¼ of the symbol rate.
12. The frequency acquisition and phase-lock loop of claim 8 , wherein the difference response signal is amplified before it is filtered.
13. The frequency acquisition and phase-lock loop of claim 8 , wherein the filtered difference response signal is amplified before it is returned to the VCO.