IP Library Granted Patent US 7,745,266
Granted Patent B2
US 7,745,266 · App. 11/318,637 · Granted Jun 29, 2010

Method of forming a fuse part

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Quick Facts
Patent No.
US 7,745,266
App. No.
11/318,637
Granted
Jun 29, 2010
Kind
B2
Abstract

The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.

Claims (20)

1. A method of forming a fuse part in a semiconductor device, comprising:

forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, wherein the selective metal layer completely covers the via hole and the metal line;

forming a fuse metal layer on the selective metal layer, the fuse metal layer electrically connecting at least two metal lines with each other, wherein the at least two metal lines are located in a same layer; and

forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.

2. The method of claim 1 , wherein the metal line is formed by a dual damascene process.

3. The method of claim 1 , wherein the selective metal layer is composed of W, Ti, TiN, Ta, or TaN.

4. The method of claim 1 , wherein the fuse metal layer is composed of Ti, TiN, Ta, or TaN.

5. The method of claim 1 , wherein the metal line and the fuse metal layer are connected to each other through the selective metal layer.

6. A method of forming a fuse part in a semiconductor device, comprising:

forming a first insulation layer on a metal line in a semiconductor device;

forming a first photosensitive layer pattern on the first insulation layer in order to form a fuse part;

etching the first insulation layer by using the first photosensitive layer pattern to a degree that the metal line is exposed;

selectively forming a selective metal layer on the exposed metal line, wherein the selective metal layer completely covers an interconnecting part between the metal line and the fuse metal layer and the metal line;

forming a fuse metal layer on the selective metal layer, the fuse metal layer electrically connecting at least two metal lines with each other, wherein the at least two metal lines are located in a same layer;

forming a fuse metal layer pattern by using a second photosensitive layer pattern which is formed on the fuse metal layer; and

forming a second metal insulation layer on the fuse metal layer pattern.

7. The method of claim 6 , wherein the first insulation layer is formed as a nitride- or oxide-based layer.

8. The method of claim 7 , wherein the selective metal layer is composed of W, Ti, TiN, Ta, or TaN.

9. The method of claim 6 , wherein the fuse metal layer is composed of Ti, TiN, Ta, or TaN.

10. The method of claim 6 , wherein the metal line and fuse metal layer are connected to each other through the selective metal layer.

Assignments (2)
CHANGE OF NAME Recorded Jul 12, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018094/0024 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2005
From: BAE, SE-YEUL
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017424/0564 →