Granted Patent B2

US 7,517,769 · App. 11/319,075 · Granted Apr 14, 2009

Abstract

Claims (55)

1. A method for integrally forming a capacitor and a microcoil on a semiconductor substrate, the method comprising:

depositing and patterning a dielectric layer on the substrate;

depositing and patterning a sacrificial layer on the substrate;

depositing and patterning conductive material on the semiconductor substrate, the patterned conductive material including a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode portion of the capacitor;

depositing and patterning a polymer layer on the semiconductor substrate;

removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil;

depositing a second conductive material on exposed portions of the conductive material; and

removing the sacrificial layer.

2. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 1 , wherein depositing and patterning the conductive material comprises forming a first winding portion associated with the microcoil and a second winding portion associated with the microcoil and forming the overlapping electrode portion between the first winding portion and the second winding portion associated with the same microcoil.

3. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 2 , wherein:

forming the overlapping electrode portion between the first winding portion and the second winding portion comprises forming a first capacitance portion and a second capacitance portion, the first capacitance portion corresponding to overlapping portions of the overlapping electrode and a first fixed electrode prefabricated on the substrate, the second capacitance portion corresponds to overlapping portions of the overlapping electrode and a second fixed electrode prefabricated on the substrate, and a distance exists between the first fixed electrode and the second fixed electrode, and

the first capacitance portion has a first capacitance and the second capacitance portion has a second capacitance, the first capacitance being equal to the second capacitance.

4. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 1 , further comprising reflowing the polymer layer after removing the exposed portion of the conductive pattern exposed by the patterned polymer layer.

5. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 1 , wherein depositing and patterning conductive material comprises stacking a plurality of metal layers.

6. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 5 , wherein the metal layer stack includes a stress engineered material.

7. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 6 , wherein the stress engineered material includes at least one of Mo, Cr, Ni, Zr and any combination thereof.

8. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 1 , wherein the substrate is a prefabricated integrated circuit including a plurality of patterned metal layers, a passivation layer and an insulating layer formed on the semiconductor substrate, and an outer surface of the prefabricated integrated circuit is planar.

9. A method for integrally forming a capacitor and a microcoil on a substrate, the method comprising:

forming and patterning a first dielectric layer on the substrate,

depositing and patterning a first conductive material on the substrate;

depositing and patterning a second dielectric material on the substrate;

depositing a second conductive material on the substrate forming at least a first portion and a second portion;

planarizing an exposed surface of the second conductive material and the patterned second dielectric material;

depositing and patterning a sacrificial layer on the planarized surface;

removing the patterned second dielectric material;

forming third conductive material on the sacrificial layer;

depositing and patterning a polymer layer on the substrate;

removing a portion of the first conductive material exposed by the patterned polymer layer to release a portion of the first conductive material from the substrate to form out-of-plane windings of the microcoil;

depositing fourth conductive material on exposed portions of the first conductive material and the third conductive material;

removing the sacrificial layer;

forming each of the first conductive material, the second conductive material and the fourth conductive material to include a first portion and a second portion corresponding to a first winding portion and a second winding portion of the same microcoil; and

forming a capacitance region in the third conductive material between the first winding portion and the second winding portion.

10. The method for integrally forming a capacitor and a microcoil on a semiconductor substrate as claimed in claim 9 , further comprising reflowing the polymer layer after removing the exposed portion of the conductive pattern exposed by the patterned polymer layer.

11. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 9 , wherein at least one of depositing and patterning the first conductive material and forming third conductive material comprises stacking a plurality of metal layers.

12. The method for integrally forming a capacitor and a microcoil on a semiconductor substrate as claimed in claim 11 , wherein the metal layer stack includes a stress engineered metal.

13. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 9 , further comprising forming a third dielectric layer before forming the sacrificial layer.

14. The method for integrally forming a capacitor and a microcoil on a substrate as claimed in claim 9 , further comprising:

providing the capacitance region with a first capacitance region and a second capacitance region separated by a portion of the second dielectric material,

wherein the first capacitance region corresponds to overlapping portions of the third conductive layer and the first winding portion,

the second capacitance region corresponds to overlapping portions of the third conductive layer and the second winding portion, and

the first capacitance region has a first capacitance and the second capacitance region has a second capacitance, the first capacitance being equal to the second capacitance.

15. A method for integrally forming a capacitance region and a microcoil on a substrate, the method comprising:

forming a first electrode and a fixed portion of a second electrode associated with the capacitance region on the substrate;

depositing and patterning a sacrificial layer on the first electrode;

depositing and patterning a conductive material on the substrate, the patterning forming a pattern corresponding to windings of the microcoil and a pattern corresponding to a moveable portion of the second electrode, the moveable portion of the second electrode connecting to the fixed portion of the second electrode;

depositing and patterning a polymer mask layer on the substrate;

removing a portion of the deposited and patterned conductive material exposed by the mask layer to release at least a portion of the windings pattern from the substrate to form out-of-plane windings of the microcoil;

depositing a second conductive material on the formed out-of-plane windings of the microcoil and the moveable portion of the second electrode;

reflowing the polymer layer after removing the exposed portion of the deposited and patterned second conductive material to allow further out-of-plane movement of the windings; and

removing the sacrificial layer forming a gap between the first electrode and the second electrode of the capacitor.

16. The method for integrally forming a capacitance region and a microcoil on a substrate as claimed in claim 15 , wherein depositing and patterning the conductive material comprises depositing and patterning a stress engineered material.

17. The method for integrally forming a capacitance region and a microcoil on a substrate as claimed in claim 15 , wherein depositing and patterning the conductive material comprises depositing and patterning at least one of a Ti layer, a MoCr layer, a Au layer, a Ni layer and any combination thereof.

18. The method for integrally forming a capacitance region and a microcoil on a substrate as claimed in claim 15 , wherein depositing and patterning the conductive material comprises depositing and patterning a plurality of metal layers.

19. The method for integrally forming a capacitance region and a microcoil on a substrate as claimed in claim 15 , wherein a distance exists between the pattern corresponding to the windings of the microcoil and the pattern corresponding to the capacitance region including the first electrode and the second electrode.

20. The method for integrally forming a capacitance region and a microcoil on a substrate as claimed in claim 15 , wherein at least a portion of the capacitance region overlaps with a portion of the formed out-of-plane windings.

Assignments (9)