Gate driver and display device having the same

1. A gate driver, comprising:

a plurality of shift registers connected in cascade to each other and driven by a plurality of multiphase clock, respectively, wherein the next shift register to which one of the plurality of multiphase clocks is applied is reset using an output signal outputted from the previous shift register in response to the one of the plurality of multiphase clocks,

wherein the output signal of each shift register is inputted into a set terminal of the first next shift register, a reset terminal of the second next shift register and a reset terminal of the previous shift register,

wherein the output signal of a current shift register sets the first next shift register and resets the second next shift register and the previous shift register.

2. The gate driver according to claim 1 , wherein the plurality of shift registers include a number N of shift registers, each of the plurality of multiphase clocks includes a two-phase clock, and the (M+2)th shift register is reset by an output signal of the Mth shift register, where M is (N−2), and M and N are integers.

3. The gate driver according to claim 1 , wherein the plurality of shift registers includes a number N of shift registers, each of the plurality of multiphase clocks includes a three-phase clock, and the (M+3)th shift register is reset by an output signal of the Mth shift register, where M is (N−3), and M and N are integers.

4. The gate driver according to claim 1 , wherein the plurality of shift registers include a number N of shift registers, each of the plurality of multiphase clocks includes a four-phase clock, and the (M+4)th shift register is reset by an output signal of the Mth shift register, where M is (N−4), and M and N are integers.

5. The gate driver according to claim 1 , wherein the plurality of shift registers include a number N of shift registers, each of the plurality of multiphase clocks includes a five-phase clock, and the (M+5)th shift register is reset by an output signal of the Mth shift register, where M is (N−5), and M and N are integers.

6. The gate driver according to claim 1 , wherein the multiphase clocks partially overlap each other.

7. A display device, comprising:

a display panel in which pixels defined by gate lines and data lines are arranged in a matrix;

a data driver supplying image data to the data lines; and

a gate driver supplying corresponding output signals to the gate lines, the gate driver including a plurality of shift registers connected in cascade to each other and driven by a plurality of multiphase clocks, respectively, wherein the next shift register to which one of the plurality of multiphase clocks is applied is reset using an output signal outputted from the previous shift register in response to the one of the plurality of multiphase clocks,

wherein the output signal of each shift register is inputted into a set terminal of the first next shift register, a reset terminal of the second next shift register and a reset terminal of the previous shift register,

wherein the output signal of a current shift register sets the first next shift register and resets the second next shift register and the previous shift register.

8. The display device according to claim 7 , wherein the plurality of shift registers includes a number N of shift registers, each of the plurality of multiphase clocks includes a two-phase clock, and the (M+2)th shift register is reset by an output signal of the Mth shift register, where M is (N−2), and M and N are integers.

9. The display device according to claim 7 , wherein the plurality of shift registers includes a number N of shift registers, each of the plurality of multiphase clocks includes a three-phase clock, and the (M+3)th shift register is reset by an output signal of the Mth shift register, where M is (N−3), and M and N are integers.

10. The display device according to claim 7 , wherein the plurality of shift registers includes a number N of shift registers, each of the plurality of multiphase clocks includes a four-phase clock, and the (M+4)th shift register is reset by an output signal of the Mth shift register, where M is (N−4), and M and N are integers.

11. The display device according to claim 7 , wherein the plurality of shift registers includes a number N of shift registers, each of the plurality of multiphase clocks includes a five-phase clock, and the (M+5)th shift register is reset by an output signal of the Mth shift register, where M is (N−5), and M and N are integers.

12. A method for driving gate lines in a display panel, comprising:

sequentially outputting a plurality of output signals, including first, second, third and fourth output signals through corresponding first, second, third and fourth shift registers, respectively;

setting the second shift register concurrently with outputting the first output signal; and

setting the third shift register and resetting the first shift register and fourth shift register concurrently with outputting the second output signal,

wherein the second output signal of the second shift register is inputted into a set terminal of the third shift register, a reset terminal of the fourth shift register and a reset terminal of the first shift register,

wherein the second output signal of the second shift register sets the third shift register and resets the fourth shift register and the first shift register,

wherein the sequentially outputting including sequentially outputting the first, second, third and fourth output signals.

13. The method of claim 12 , wherein the sequentially outputting includes outputting an N-number of output signals through a corresponding N-number of shift registers driven by a plurality of two-phase clocks, including resetting the N-numbered shift register concurrently with outputting the (N−2)-numbered output, where N is an integer.

14. The method of claim 12 , wherein the sequentially outputting includes outputting an N-number of output signals through a corresponding N-number of shift registers driven by a plurality of three-phase clocks, including resetting the N-numbered shift register concurrently with outputting the (N−3)-numbered output, where N is an integer.

15. The method of claim 12 , wherein the sequentially outputting includes outputting an N-number of output signals through a corresponding N-number of shift registers driven by a plurality of four-phase clocks, including resetting the N-numbered shift register concurrently with outputting the (N−4)-numbered output, where N is an integer.

16. The method of claim 12 , wherein the sequentially outputting includes outputting an N-number of output signals through a corresponding N-number of shift registers driven by a plurality of a K-number of clock phases, including resetting the N-numbered shift register concurrently with outputting the (N−K)-numbered output, where N and K are integers.