IP Library Granted Patent US 7,650,070
Granted Patent B2
US 7,650,070 · App. 11/320,182 · Granted Jan 19, 2010

Self-testing optical transceiver controller using internalized loopbacks

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Quick Facts
Patent No.
US 7,650,070
App. No.
11/320,182
Granted
Jan 19, 2010
Kind
B2
Abstract

An operational optical transceiver microcontroller configured to initiate a self-test using internalized loop backs. The microcontroller includes a memory, at least one processor and a number of input and output terminals. The output terminals are coupled to internally corresponding input terminals by a configurable switch. The memory receives microcode that, when executed by the processor, causes the microcontroller to close the switches so as to internally connect the output and input terminals. A signal is then asserted on the output terminal. This signal loops back and is received by the input terminal. The processor may then detect the microcontroller's response to the signal.

Claims (35)

1. An optical transceiver microcontroller comprising:

a plurality of input terminals;

a plurality of output terminals;

a memory;

at least one processor coupled to the memory so as to be capable of executing microcode from the memory during operation;

a configurable switch array that couples one of the output terminals to one of the input terminals when closed;

wherein the memory has microcode that when executed by the at least one processor, causes the at least one processor to cause the microcontroller to self-test by performing the following:

act of closing the configurable switch array;

an act of asserting an electrical signal on the output terminal;

an act of receiving the electrical signal on the input terminal through the configurable switch array; and

an act of detecting a response of the microcontroller to the received electrical signal on the input terminal.

2. An optical transceiver microcontroller in accordance with claim 1 , wherein the optical transceiver microcontroller is configured to close the configurable switch array by writing data to a register coupled to the configurable switch array.

3. An optical transceiver microcontroller in accordance with claim 1 , wherein the asserted signal is an analog signal.

4. An optical transceiver microcontroller in accordance with claim 1 , wherein the asserted signal is a digital signal.

5. An optical transceiver microcontroller in accordance with claim 1 , wherein the executed microcode is configured to direct a self-test of internal digital components of the optical transceiver microcontroller.

6. An optical transceiver microcontroller in accordance with claim 1 , wherein the executed microcode is configured to direct a self-test of internal analog components of the optical transceiver microcontroller.

7. An optical transceiver microcontroller in accordance with claim 6 , wherein the internal analog components are one or more of a sensor, a multiplexer, an analog-to-digital converter, a high-speed comparator, or a digital-to-analog converter.

8. An optical transceiver microcontroller in accordance with claim 1 , wherein the executed microcode is configured to direct a self-test of logical functional blocks of the optical transceiver microcontroller.

9. An optical transceiver microcontroller in accordance with claim 8 , wherein the logical functional blocks are one of a host communication interface or an external device interface.

10. An optical transceiver microcontroller in accordance with claim 1 , wherein the executed microcode is configured to direct a self-test of the response of the optical transceiver microcontroller to output signals looped back to one of the plurality of input terminals.

11. In an optical transceiver microcontroller including a plurality of input terminals, a plurality of output terminals, a memory, at least one processor, and a configurable switch array, a method for the optical transceiver microcontroller to perform a self-test, the method comprising:

an act of executing microcode from the memory, wherein the microcode is structured such that when executed by the at least one processor, causes the optical transceiver microcontroller to perform the following:

an act of closing the configurable switch array so as to couple one of the output terminals to one of the input terminals;

an act of asserting an electrical signal on the output terminal;

an act of receiving the electrical signal on the input terminal through the configurable switch array; and

an act of detecting a response of the microcontroller to the received electrical signal on the input terminal.

12. A method in accordance with claim 11 , wherein the asserted signal is an analog signal.

13. A method in accordance with claim 11 , wherein the asserted signal is a digital signal.

14. A method in accordance with claim 11 , wherein the executed microcode directs a self-test of internal analog components of the optical transceiver microcontroller.

15. A method in accordance with claim 14 , wherein the internal analog components are one or more of a sensor, a multiplexer, an analog-to-digital converter, a high-speed comparator, or a digital-to-analog converter.

16. A method in accordance with claim 11 , wherein the executed microcode directs a self-test of logical functional blocks of the optical transceiver microcontroller.

17. A method in accordance with claim 16 , wherein the logical functional blocks are one of a host communication interface or an external device interface.

18. A method in accordance with claim 11 , wherein the executed microcode directs a self-test of the response of the optical transceiver microcontroller to external signals.

19. A method in accordance with claim 11 , wherein the executed microcode directs a self-test of internal digital components of the optical transceiver microcontroller.

20. A method in accordance with claim 11 , wherein the memory receives the microcode from a host computing system that is coupled to the microcontroller or from an optical transceiver persistent memory that is coupled to the microcontroller.

Assignments (4)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →