Multi-level memory cell sensing
A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.
1. A memory circuit comprising:
a plurality of memory cell transistors having programmable threshold voltages, each of the plurality of memory cell transistors having a gate node and a drain node;
a wordline coupled to gate nodes of the plurality of memory cell transistors;
a circuit to apply a sequence of voltages on the wordline during a read cycle of the plurality of memory cells, wherein voltages in the sequence of voltages are between the programmable threshold voltages;
a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding drain node of the plurality of memory cell transistors;
a current mirror circuit coupled to each of the plurality of sense amplifiers to provide a substantially constant current to be compared against currents flowing in the drain nodes of the memory cell transistors during the read cycle;
a plurality of latches coupled to store data when output nodes of the plurality of sense amplifiers change state; and
a control circuit to control the application of the sequence of voltages on the wordline, and to provide data to the plurality of latches.
2. The memory circuit of claim 1 wherein the current mirror circuit comprises a plurality current reference circuits coupled in parallel.
3. The memory circuit of claim 2 wherein each of the plurality of current reference circuits include a transistor having a programmable threshold voltage.
4. The memory circuit of claim 1 further comprising a sample and hold circuit coupled between the current mirror circuit and the plurality of sense amplifiers.
5. The memory circuit of claim 1 further comprising an x-decoder having output circuits coupled to receive the sequence of voltages on a power supply node.
6. The memory circuit of claim 5 wherein the power supply node is coupled to electrically float prior to providing the sequence of voltages.
7. The memory circuit of claim 5 wherein the control circuit is coupled to cause the power supply node to pre-charge and then to electrically float prior to providing the sequence of voltages.