IP Library Granted Patent US 7,528,063
Granted Patent B2
US 7,528,063 · App. 11/320,625 · Granted May 5, 2009

Semiconductor device having a reductant layer and manufacturing method thereof

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Quick Facts
Patent No.
US 7,528,063
App. No.
11/320,625
Granted
May 5, 2009
Kind
B2
Abstract

A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a metal line layer formed by depositing a second metal on the reductant layer.

Claims (21)

1. A method of manufacturing a semiconductor device, comprising:

preparing a substrate where an inter-metal dielectric is formed on the top thereof;

etching the inter-metal dielectric to form a via hole exposing a portion of the substrate;

forming a via plug by filling the via hole with a first metal;

forming a reductant layer by coating a layer of hafnium (Hf) on the via plug to a predetermined thickness; and

forming a metal line layer by depositing a second metal on the reductant layer and the inter-metal dielectric.

2. The method according to claim 1 , further comprising forming a barrier layer on the inter-metal dielectric and the exposed portion of the substrate after the formation of the via hole.

3. The method according to claim 1 , further comprising planarizing an upper portion of the via plug and an upper portion of the inter-metal dielectric after the formation of the via plug.

4. The method according to claim 1 , further comprising performing a thermal treatment in a nitrogen ambient after the formation of the metal line layer.

5. The method according to claim 1 , wherein the layer of hafnium has a reducing power higher than that of the first metal.

6. The method according to claim 1 , wherein the layer of hafnium is formed by using a chemical vapor deposition (CVD) process.

7. The method according to claim 1 , wherein the via plug is formed by depositing the first metal using a CVD process.

8. The method according to claim 1 , wherein the metal line layer is formed by depositing the second metal using a CVD process.

9. A method of manufacturing a semiconductor device, comprising:

preparing a substrate where an inter-metal dielectric is formed on the top thereof;

etching the inter-metal dielectric to form a via hole exposing a portion of the substrate;

forming a via plug by selectively depositing a first metal into the via hole;

forming a reductant layer by coating a layer of hafnium on the via plug to a predetermined thickness;

forming a metal line layer by non-selectively depositing a second metal on the reductant layer and the inter-metal dielectric; and

monocrystallizing the first metal and the second metal in a direction identical to a crystallization direction of the substrate by heating the substrate at predetermined pressure and temperature for a predetermined time.

10. The method according to claim 9 , further comprising forming a barrier layer on the inter-metal dielectric and the exposed portion of the substrate after the formation of the via hole.

Assignments (2)
CHANGE OF NAME Recorded Jul 13, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018099/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2005
From: KIM, JUNG JOO
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017426/0396 →