Semiconductor device and method of manufacturing the same
View Patent ↗A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
1. A method of manufacturing a semiconductor device on a wafer including a scribe lane region and chip region, comprising:
forming a first pad including a first metal and an inter-connection line including the first metal in the scribe lane region;
forming a second pad including the first metal in the chip region;
sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad;
exposing the first and second pads by patterning the etch-stop layer and the first insulation layer;
forming third and fourth pads including a second metal on the first and second pads;
sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and
etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
2. The method of claim 1 , wherein the first metal is copper.
3. The method of claim 1 , wherein the second metal is aluminum.
4. The method of claim 1 , wherein the etch-stop layer has a different etching rate than the first, second, and third insulation layers.
5. The method of claim 4 , wherein forming the etch-stop layer comprises forming a layer of a nitride.
6. The method of claim 4 , wherein the etch-stop layer has a thickness such that the second pad is not exposed when the first, second, and third insulation layers are etched.
7. The method of claim 1 , wherein forming the first and second insulation layers comprise forming layers of an oxide.
8. The method of claim 6 , wherein forming the first and second insulation layers comprise forming layers of an oxide.
9. The method of claim 1 , wherein forming the third insulation layer comprises forming a layer of nitride.
10. The method of claim 6 , wherein forming the third insulation layer comprises forming a layer of nitride.
11. The method of claim 1 , wherein the second and third insulation layers are passivation layers.
12. The method of claim 6 , wherein the second and third insulation layers are passivation layers.