Semiconductor integrated circuit having discrete trap type memory cells
View Patent ↗A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
1. A semiconductor device comprising:
a plurality of memory cells each of which includes:
a first diffusion region formed in a semiconductor substrate;
a second diffusion region formed in the semiconductor substrate;
a first gate electrode formed over a region of semiconductor substrate between the first and second diffusion regions;
a second gate electrode formed over the region of semiconductor substrate between the first and second diffusion regions;
a charge storage film formed over the region of semiconductor substrate between the first and second diffusion regions, having discrete traps, and located between the first and second gate electrodes; and
a third gate electrode formed over the charge storage film;
a word line coupled to the third gate electrodes of the plurality of memory cells which are arranged in a first direction; and
a bit/source line coupled to first diffusion regions of the plurality of memory cells which are arranged in a second direction intersecting the first direction,
wherein the first gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other, and
wherein the second gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other.
2. A semiconductor device according to claim 1 , wherein each of the first and second gate electrodes has a width smaller than a technology feature size.
3. A semiconductor device according to claim 1 , wherein the charge storage film is a silicon nitride film.
4. A semiconductor device according to claim 1 , wherein one of the plurality of memory cells shares the bit line/source line and the first diffusion region with a neighboring one of the plurality of memory cells.
5. A semiconductor device according to claim 1 , wherein the bit/source line is a diffusion layer line.
6. A semiconductor device according to claim 1 , wherein the first gate electrode is located closer to the first diffusion region then the second diffusion region;
wherein the charge storage film has a first portion and a second portion to store two bits, the first portion being located closer to the first gate electrode than the second gate electrode and the second portion being located closerto the second gate electrode than the first gate electrode;
wherein in a write operation to the first portion, current flows from the first diffusion region to the second diffusion region; and
wherein in a read operation from the first portion, current flows from the first diffusion region to the second diffusion region.
7. A semiconductor device according to claim 6 , wherein in an erase operation, electrons held in both of the first and second portions are extracted into the third gate electrode.
8. A semiconductor device comprising:
a plurality of memory cells each of which includes:
a first diffusion region formed in a semiconductor substrate:
a second diffusion region formed in the semiconductor substrate;
a first charge storage film having discrete traps and formed over a region of semiconductor substrate between the first and second diffusion regions;
a second charge storage film having discrete traps and formed over the region of semiconductor substrate between the first and second diffusion regions;
a first gate electrode formed over the first charge storage film;
a second gate electrode formed over the second charge storage film; and
a third gate electrode formed over the region of semiconductor substrate between the first and second diffusion regions and located between the first and second charge storage film;
a word line coupled to the first and second gate electrodes of the plurality of memory cells which are arranged in a first direction; and
a bit/source line coupled to the first diffusion regions of the plurality of memory cells which are arranged in a second direction intersecting the first direction.
9. A semiconductor device according to claim 8 , wherein each of the first and second charge storage films is a silicon nitride film.
10. A semiconductor device according to claim 8 , wherein one of the plurality of memory cells shares the bit line/source line and the first diffusion region with a neighboring one of the plurality of memory cells.
11. A semiconductor device according to claim 8 , wherein the bit/source line is a diffusion layer line.
12. A semiconductor device according to claim 8 , wherein the first charge storage film is located closer to the first diffusion region then the second diffusion region and the second charge storage film is located closer to the second diffusion region than the first diffusion region;
wherein in a write operation to the first charge storage film, current flows from the second diffusion region to the first diffusion region; and
wherein in a read operation from the first operation, current flows the first diffusion region to the second diffusion region.
13. A semiconductor device according to claim 12 , wherein in an erase operation, electrons held in both of the first and second charge storage film are extracted into the third gate electrode.