Semiconductor device and manufacturing method thereof to prevent a notch
View Patent ↗A method for manufacturing a semiconductor device includes: preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed; forming a first via plug and a first metal line by filling the first via hole and the first trench with a first metal; planarizing the first metal line and the first interlayer insulation layer; forming a second interlayer insulation layer on the first metal line and the first interlayer insulation layer; planarizing the second interlayer insulation layer; forming a second via hole and a second trench in the second interlayer insulation layer; forming a second via plug and a second metal line by filling the second via hole and the second trench with a second metal; and planarizing the second metal line and the second interlayer insulation layer.
1. A method of manufacturing a semiconductor device, comprising:
preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed;
forming a first via plug and a first metal line by filling the first via hole and the first trench with a first metal;
performing a first CMP process of planarizing the first metal line and the first interlayer insulation layer;
forming a second etch stop layer on the first metal line and the first interlayer insulation layer;
performing a CMP process of planarizing the second etch stop layer;
forming a second interlayer insulation layer on the planarized second etch stop layer;
performing a second CMP process of planarizing the second interlayer insulation layer;
forming a second via hole and a second trench in the second interlayer insulation layer;
forming a second via plug and a second metal line by filling the second via hole and the second trench with a second metal; and
performing a third CMP process of planarizing the second metal line and the second interlayer insulation layer.
2. The method according to claim 1 , wherein the first metal is copper (Cu).
3. The method according to claim 1 , wherein the second CMP process is preformed to planarize the second interlayer insulation layer until removing a notch formed on the surface of the second interlayer insulation, which is caused by a transfer of scratched formed on the surface of the first metal line.
4. The method according to claim 1 , wherein the forming of the first interlayer-insulation layer comprises:
forming a first etch stop layer on the substrate; and
forming at least one insulation layer on the first etch stop layer.
5. The method according to claim 1 , wherein the first via hole is formed after the first trench is formed, and the second via hole is formed is formed after the second trench is formed.
6. The method according to claim 1 , wherein the first trench is formed after the first via hole is formed, and the second trench is formed after the second via hole is formed.
7. A method of manufacturing a semiconductor device, comprising:
preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed;
forming a first via plug and a first metal line by filling the first via hole and the first trench with a first metal;
performing a first CMP process of planarizing the first metal line and the first interlayer insulation layer;
forming a second etch stop layer on the first metal line and the first interlayer insulation layer;
performing a CMP process of planarizing the second etch stop layer;
forming a second interlayer insulation layer on the planarized second etch stop layer;
performing a second CMP process of planarizing the second interlayer insulation layer;
forming a third interlayer insulation layer on the second interlayer insulation layer;
forming a second via hole and a second trench in the third interlayer insulation layer;
forming a second via plug and a second metal line by filling the second via hole and the second trench with a second metal; and
performing a third CMP process of planarizing the second metal line and the third interlayer insulation layer.
8. The method according to claim 7 , wherein the first metal is copper (Cu).
9. The method according to claim 7 , wherein the second CMP process is preformed to planarize the second interlayer insulation layer until removing a notch formed on the surface of the second interlayer insulation, which is caused by a transfer of scratched formed on the surface of the first metal line.
10. The method according to claim 7 , wherein the forming of the first interlayer insulation layer comprises:
forming a first etch stop layer on the substrate; and
forming at least one insulation layer on the first etch stop layer.
11. The method according to claim 7 , wherein the forming of the third interlayer insulation layer comprises forming at least one insulation layer on the second insulation layer.
12. The method according to claim 7 , wherein the first via hole is formed in the first insulation layer after the first trench is formed, and the second via hole is formed after the second trench is formed.
13. The method according to claim 7 , wherein the first trench is formed in the first interlayer insulation layer after the first via hole is formed, and the second trench is formed after the second via hole is formed.