Directory-based data transfer protocol for multiprocessor system
View Patent ↗A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.
1. A method for maintaining data coherency in a multiprocessor system, comprising the steps of:
determining that a data line is not found in a cache of a first processor;
forwarding a request for the data line to a second processor;
forwarding the data line from the second processor to the first processor;
updating a directory of the second processor to reflect the data line being forwarded to the first processor; and
forwarding a directory update message to at least one additional processor separate from the first and second processor to reflect the data line being forwarded to the first processor.
2. The method of claim 1 , further comprising the step of determining that an entry having an address of the data line is not found in a directory of the first processor.
3. The method of claim 2 , wherein an entry in the directory of the first processor includes a memory address, a most recent data holder, and a line state.
4. The method of claim 2 , wherein the second processor is a home agent of the data line.
5. The method of claim 1 , further comprising the step of determining that an entry for an address of the data line is found in a directory of the first processor.
6. The method of claim 5 , wherein an entry in the directory of the first processor includes a memory address, a most recent data holder, and a line state.
7. The method of claim 5 , wherein the address of the data line indicates that the second processor is a data holder.
8. The method of claim 5 , further comprising the step of invalidating the entry for the address of the data line in the directory of the first processor after the first processor receives the data line from the second processor.
9. The method of claim 1 , further comprising the step of updating a directory of the at least one additional processor to reflect the data line being forwarded to the first processor responsive to the at least one additional processor receiving the directory update message.
10. The method of claim 1 , wherein an entry in the directory includes a memory address, a most recent data holder, and a line state.