Multi-stage finite impulse response filter processing
In one aspect, the invention is a method of emulating an n-stage finite impulse response (FIR) filter. The method includes connecting an output of a one-stage FIR filter to an input of the one-stage FIR filter to form a feedback path. The method also includes configuring the one-stage FIR filter to send a feedback signal along the feedback path. The feedback signal corresponds to an output data signal from at least one of a first stage of the n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
1 . A method of emulating an n-stage finite impulse response (FIR) filter, the method comprising:
connecting an output of a one-stage finite impulse response (FIR) filter to an input of the one-stage FIR filter to form a feedback path; and
configuring the one-stage FIR filter to send a feedback signal along the feedback path, the feedback signal corresponding to an output data signal from at least one of a first stage of the n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
2 . The method of claim 1 , further comprising combining the feedback signal with an input signal to provide an input to the one-stage FIR filter.
3 . The method of claim 2 , further comprising configuring the one-stage FIR filter to emulate n stages of the n-stage FIR filter using the feedback data and the input data.
4 . The method of claim 1 , further comprising configuring the one-stage FIR filter to:
generate first stage output data corresponding to an output of a first stage of the n-stage FIR filter; and
if a sufficient number of the first stage output data is received, generate at least a portion of second stage output data corresponding to a second stage of the n-stage FIR filter before generating further first stage output data.
5 . The method of claim 4 , further comprising configuring the one-stage FIR filter to:
generate the further first stage output data; and
if a sufficient number of the further first stage output data is generated, generate further second stage output data.
6 . The method of claim 5 , further comprising configuring the one-stage FIR filter to:
if a sufficient number of an (n−1)th stage output data corresponding to a (n−1)th stage of the n-stage FIR filter is generated, generate nth stage output data corresponding to an nth stage of the n-stage FIR filter; and
send the nth stage output data to an output device.
7 . The method of claim 1 , further comprising configuring the one-stage FIR filter to generate second stage output data corresponding to a second stage of the n-stage FIR filter after generating first stage output data corresponding to a first stage of the n-stage FIR filter.
8 . The method of claim 1 , further comprising configuring the one-stage FIR filter to emulate the n stages of the n-stage FIR filter based on decimation ratios selected by a user.
9 . The method of claim 1 , further comprising configuring the one-stage FIR filter to emulate the n stages of the n-stage FIR filter based on tap parameters selected by a user.
10 . The method of claim 1 , further comprising configuring the one-stage FIR filter to emulate the n stages of the n-stage FIR filter based on a number of stages selected by a user.
11 . The method of claim 1 , further comprising further comprising configuring the one-stage FIR filter to send output data corresponding to the nth stage of the n-stage FIR filter to an output device.
12 . An article comprising a machine-readable medium that stores executable instructions for emulating an n-stage finite impulse response (FIR) filter, the instructions causing a machine to:
connect an output of a one-stage finite impulse response (FIR) filter to an input of the one-stage FIR filter to form a feedback path; and
configure the one-stage FIR filter to send a feedback signal along the feedback path, the feedback signal corresponding to an output data signal from at least one of a first stage of the n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
13 . The article of claim 12 , further comprising instructions causing a machine to:
generate first stage output data corresponding to an output of a first stage of the n-stage FIR filter; and
if a sufficient number of the first stage output data is received, generate at least a portion of second stage output data corresponding to a second stage of the n-stage FIR filter before generating further first stage output data.
14 . The article of claim 13 , further comprising instructions causing a machine to:
if a sufficient number of an (n−1)th stage output data corresponding to a (n−1)th stage of the n-stage FIR filter is generated, generate nth stage output data corresponding to an nth stage of the n-stage FIR filter; and
send the nth stage output data to an output device.
15 . The article of claim 12 , further comprising instructions causing a machine to configure the one-stage FIR filter to generate second stage output data corresponding to a second stage of the n-stage FIR filter after generating first stage output data corresponding to a first stage of the n-stage FIR filter.
16 . An apparatus comprising:
a memory that stores executable instructions for emulating an n-stage finite impulse response (FIR) filter; and
a processor that executes the instructions to:
connect an output of a one-stage finite impulse response (FIR) filter to an input of the one-stage FIR filter to form a feedback path; and
configure the one-stage FIR filter to send a feedback signal along the feedback path, the feedback signal corresponding to an output data signal from at least one of a first stage of the n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
17 . The apparatus of claim 16 , further comprising instructions to:
generate first stage output data corresponding to an output of a first stage of the n-stage FIR filter; and
if a sufficient number of the first stage output data is received, generate at least a portion of second stage output data corresponding to a second stage of the n-stage FIR filter before generating further first stage output data.
18 . The apparatus of claim 17 , further comprising to:
if a sufficient number of an (n−1)th stage output data corresponding to a (n−1)th stage of the n-stage FIR filter is generated, generate nth stage output data corresponding to an nth stage of the n-stage FIR filter; and
send the nth stage output data to an output device.
19 . The apparatus of claim 16 , further comprising instructions to configure the one-stage FIR filter to generate second stage output data corresponding to a second stage of the n-stage FIR filter after generating first stage output data corresponding to a first stage of the n-stage FIR filter.
20 . A finite impulse response (FIR) filter having an input and an output, the FIR filter comprising:
a sample memory configured to receive sample data from the input of the FIR filter and feedback data;
an adder coupled to receive data from the sample memory;
a coefficient memory, configured to store FIR filter coefficient values, each of the FIR filter coefficient values corresponding to filter coefficient values for a particular stage of an n-stage FIR filter;
a multiplier configured to receive the sample data from the adder and the FIR filter coefficient values from the coefficient memory and to combine the sample data and the FIR filter coefficient values to generate a product signal;
an accumulator adapted to receive the product signal from the multiplier at an input thereof and to provide a FIR filter stage output signal corresponding to at least one of n stages of the n-stage FIR filter at an output thereof; and
a feedback signal path coupled between the output of the accumulator and the input of the sample memory and configured to provide the feedback data.
21 . The FIR filter of claim 20 wherein the sample memory comprises an odd sample memory portion and even sample memory portion.
22 . The FIR filter of claim 20 wherein the FIR filter is configured to send a feedback data along the feedback path, the feedback data corresponding to the FIR filter stage output signal from at least one of a first stage of an n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
23 . The FIR filter of claim 20 further comprising a controller coupled to the adder to control the data values provided to the multiplier from the adder, to the coefficient memory to control the coefficient memory values provided to the multiplier from the coefficient memory, and to the sample memory to control the sample data provided to the adder.
24 . A receiver in a side object detection system disposed in a vehicle, the receiver comprising:
an analog-to-digital converter comprising a finite impulse response (FIR) filter, the FIR comprising:
a sample memory configured to receive sample data from an input of the FIR filter and feedback data;
an adder coupled to receive data from the sample memory;
a coefficient memory configured to store FIR filter coefficient values, each of the FIR filter coefficient values corresponding to filter coefficient values for a particular stage of an n-stage FIR filter;
a multiplier configured to receive the sample data from the adder and the FIR filter coefficient values from the coefficient memory and to combine the sample data and the FIR filter coefficient values provided thereto to provide a product signal;
an accumulator configured to receive the product signal from the multiplier circuit at an input thereof and to provide a FIR filter stage output signal corresponding to at least one of n stages of the n-stage FIR filter at an output thereof; and
a feedback signal path coupled between the output of the accumulator and the input of the sample memory and configured to provide the feedback data.
25 . The receiver of claim 24 wherein the sample memory comprises an odd sample memory portion and even sample memory portion.
26 . The receiver of claim 24 wherein the receiver is configured to send a feedback data along the feedback path, the feedback data corresponding to the FIR filter stage output signal from at least one of a first stage of an n-stage FIR filter through an n−1 stage of the n-stage FIR filter.
27 . The receiver of claim 24 further comprising a controller coupled to the adder to control the data values provided to the multiplier from the adder, to the coefficient memory to control the coefficient memory values provided to the multiplier from the coefficient memory, and to the sample memory to control the sample data provided to the adder.