Method for fabricating semiconductor device
Provided is a method for fabricating a semiconductor device, capable of increasing a contact open margin and minimizing a shoulder loss of a gate line. The method includes: forming a gate line on a substrate, the gate line including a first hard mask and a second hard mask; forming an inter-layer insulating layer over the substrate and the gate line; stacking a contact mask and an anti-reflective coating layer on the inter-layer insulating layer, the contact mask defining a contact region; and etching the contact mask and the anti-reflective coating layer until the first and second hard masks are exposed.
1 . A method for fabricating a semiconductor device, comprising:
forming a gate line on a substrate, the gate line including a first hard mask and a second hard mask;
forming an inter-layer insulating layer over the substrate and the gate line;
stacking a contact mask and an anti-reflective coating layer on the inter-layer insulating layer, the contact mask defining a contact region; and
etching the contact mask and the anti-reflective coating layer until the first and second hard masks are exposed.
2 . The method of claim 1 , wherein the contact mask has an etch selectivity with respect to the second hard mask.
3 . The method of claim 2 , wherein the etch selectivity of the contact mask to the second hard mask ranges between approximately 3:1 and approximately 2:1.
4 . The method of claim 1 , wherein the forming of the gate line includes:
stacking a gate oxide layer and a gate conductive layer;
forming the first hard mask to a first thickness; and
forming the second hard mask to a second thickness.
5 . The method of claim 4 , wherein the gate conductive layer has a stack structure of a polysilicon layer and a silicide layer.
6 . The method of claim 4 , wherein the first hard mask and the second hard mask are deposited in-situ.
7 . The method of claim 1 , wherein the first hard mask has a Si—N structure and the second hard mask has a Si—O—N structure.
8 . The method of claim of claim 7 , wherein the first hard mask is formed using a gas of SiH 4 /NH 3 /N 2 .
9 . The method of claim 8 , wherein the first thickness is in a range from approximately 1,300 Å to approximately 1,600 Å.
10 . The method of claim 7 , wherein the second gate hard mask is formed using a gas of SiH 4 /N 2 O/He.
11 . The method of claim 10 , wherein the second thickness is in a range from approximately 900 Å to approximately 1,200 Å.
12 . The method of claim 1 , wherein the inter-layer insulating layer includes at least one layer selected from the group consisting of a borosilicate glass (BSG) layer, a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a tetraethyl orthosilicate (TEOS) layer, a high density plasma (HDP) oxide layer, a spin on glass (SOG) layer, and an advanced planarization layer (APL).
13 . The method of claim 1 , wherein the inter-layer insulating layer is formed using an inorganic or organic based low-permittivity layer.
14 . The method of claim 1 , wherein the inter-layer insulating layer is planarized using a chemical mechanical polishing (CMP) process or an etch-back process.
15 . The method of claim 1 , further comprising etching the inter-layer insulating layer to form a hole.