Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same
View Patent ↗In an array substrate, an LCD panel having the same and an LCD device having the same, the array substrate may include an insulating substrate, a switching element (e.g., a transistor such as a TFT), a main pixel portion, a coupling capacitor and a sub-pixel portion. The switching element may be formed on the insulating substrate in a pixel region defined by gate and data lines adjacent to each other. The gate and data lines may be formed on the insulating substrate. The main pixel portion is on a first (e.g., central) portion of the pixel region. The coupling capacitor is electrically connected to the switching element. The coupling capacitor is on the insulating substrate. The sub-pixel portion is electrically connected to the coupling capacitor. The sub-pixel portion is on a second (e.g., peripheral) portion of the pixel region. Therefore, an image display quality is improved.
1. An array substrate comprising:
an insulating substrate;
a switch on the insulating substrate in a pixel region, the pixel region defined by a first gate line and an adjacent first data line, the first gate line and the first data line being on the insulating substrate;
a main pixel portion on the pixel region, the main pixel portion including a main capacitance;
a coupling capacitor, the coupling capacitor having a first end electrically connected to the switch;
a sub-pixel portion, the sub-pixel portion including at least one capacitance electrically connected to a second end of the coupling capacitor; and
wherein the first gate line overlaps a portion of the sub-pixel portion without overlapping the main pixel region.
2. The array substrate of claim 1 , wherein a plurality of opening patterns is formed on the main pixel portion.
3. The array substrate of claim 1 , wherein a plurality of opening patterns is formed on the sub-pixel portion.
4. The array substrate of claim 1 , wherein the main pixel portion divides the pixel region into two regions along the first gate line.
5. The array substrate of claim 1 , wherein the main pixel portion is electrically connected to the switch, and wherein the switch comprises a transistor.
6. The array substrate of claim 1 , wherein the main pixel portion comprises:
a second coupling pattern on the insulating substrate; and
a main electrode on the second coupling pattern, the main electrode being electrically connected to the second coupling pattern.
7. The array substrate of claim 6 , wherein the sub-pixel portion comprises:
a first lower storage pattern on the insulating substrate;
a first sub-electrode on the first lower storage pattern, the first sub-electrode being electrically connected to the first lower storage pattern;
a second lower storage pattern on the insulating substrate; and
a second sub-electrode spaced apart from the first sub-electrode on the second lower storage pattern, the second sub-electrode being electrically connected to the second lower storage pattern.
8. The array substrate of claim 7 , wherein two Y-shaped opening patterns are formed on the main electrode, and wherein each of the Y-shaped opening patterns is symmetrical with respect to a central line of the pixel region in a horizontal direction of the pixel region.
9. The array substrate of claim 8 , wherein two linear opening patterns that are substantially parallel to one of two adjacent rods of each of the Y-shaped opening patterns are formed on the first sub-electrode.
10. The array substrate of claim 9 , wherein two linear opening patterns that are substantially parallel to another of the two adjacent rods of each of the Y-shaped opening patterns are formed on the second sub-electrode, and wherein the two linear opening patterns that are formed on the first sub-electrode are symmetrical to the two linear opening patterns that are formed on the second sub-electrode with respect to the central line of the pixel region in the horizontal direction of the pixel region.
11. The array substrate of claim 1 , wherein the main capacitance
comprises a main liquid crystal capacitance.
12. The array substrate of claim 11 , wherein the main capacitance further
comprises a main storage capacitance.
13. The array substrate of claim 1 , wherein the at I east one capacitance comprises a liquid crystal capacitance of the sub-pixel portion.
14. The array substrate of claim 13 , wherein the at least one capacitance further comprises a storage capacitance of the sub-pixel portion.
15. The array substrate of claim 1 , wherein the pixel region is further defined by a second gate line consecutive to the first gate line on the insulating substrate and a second data line consecutive to the first data line on the insulating substrate.
16. An array substrate comprising:
an insulating substrate having a pixel region, the pixel region being defined by main gate lines and source lines;
a main switch on the insulating substrate, the main switch being electrically connected to one of the main gate lines;
a main pixel portion positioned on a central portion of the pixel region, the main pixel portion being electrically connected to the main switch;
a sub-gate line on the pixel region;
a sub-switch on the insulating substrate, the sub-switch being electrically connected to the sub-gate line; and
a sub-pixel portion being on a peripheral portion of the pixel region.
17. The array substrate of claim 16 , further comprising:
a first lower storage pattern on the insulating substrate in substantially perpendicular to the gate line; and
a first coupling pattern that divides the pixel region into two regions along a horizontal direction of the pixel region, the first coupling pattern being electrically connected to the first lower storage pattern adjacent to a right side of the unit pixel.