Apparatus for generating clock signal in mobile communication terminal
View Patent ↗Disclosed is an apparatus for generating a stable clock signal having a Long term jitter noise removed therefrom. In a mobile communication terminal having a power management chip for converting a sinusoidal wave oscillated in a crystal into a clock signal of square wave, the sinusoidal wave is converted into a square wave clock signal by the stabilized driving power having no alternating current components, and thus a power noise of the square wave clock signal is removed. Then, the square wave clock signal having the power noise removed therefrom is outputted after a predetermined delay time. Accordingly, it is possible to supply the clock signal having the Long term jitter noise removed therefrom and synchronized to each device in the mobile communication terminal.
1. An apparatus for generating a clock signal in a mobile communication terminal, the apparatus comprising:
a clock signal generating section for outputting a sinusoidal wave clock signal having an extremely low oscillating frequency;
a surge current preventing section for removing a surge current of the sinusoidal wave clock signal;
a square wave converting section for converting the sinusoidal wave clock signal having the surge current removed therefrom into a square wave clock signal using a driving power having no alternating current components;
a power noise removing section for removing a power noise included in the square wave clock signal outputted from the square wave converting section; and
a clock signal error correcting section for receiving the square wave clock signal outputted from the power noise removing section and outputting the received square wave clock signal after a predetermined delay time.
2. The apparatus according to claim 1 , wherein the clock signal generating section comprises,
a crystal oscillating part for outputting a sinusoidal wave using a crystal oscillator;
an amplifying part for amplifying the sinusoidal wave outputted from the crystal oscillating part to a predetermined level; and
an automatic gain control for controlling a gain of the sinusoidal wave outputted from the amplifying part.
3. The apparatus according to claim 1 , wherein the square wave converting section comprises,
a power stabilizing part for removing an alternating current component of voltage signal components received from a driving power and maintaining a rated voltage; and
a Schmitt trigger for converting the sinusoidal wave having the surge current removed therefrom into a square wave clock signal, wherein the Schmitt trigger is driven by the driving power having the alternating current component removed therefrom.
4. The apparatus according to claim 3 , wherein the power stabilizing part comprises,
a MOS transistor serving as a diode, whose gate and source is commonly applied with the driving power; and
a capacitor for removing the alternating current component of the driving power, wherein the capacitor has an end connected to a ground and the other end connected to a drain of the transistor.
5. The apparatus according to claim 1 , wherein the surge current preventing section comprises a capacitor having an end connected to a ground and the other end connected to an input terminal of the square wave converting section.
6. The apparatus according to claim 1 , wherein the power noise removing section comprises,
a BJT transistor serving as a diode, whose base and collector are commonly connected and emitter is connected to a ground; and
a capacitor having an end commonly connected to the collector of the BJT transistor and the other end connected to a ground and removing an alternating current component of the square wave clock signal outputted from the square wave converting section.
7. The apparatus according to claim 1 , wherein the clock signal error correcting section comprises,
a resistance having an end connected to an output terminal of the power noise removing section; and
a capacitor having an end connected to the other end of the resistance and the other end connected to a ground.
8. An apparatus for generating a clock signal in a mobile communication terminal, the apparatus comprising:
an oscillating section for outputting a sinusoidal wave having a medium oscillating frequency;
a divider for dividing an output of the oscillating section in a predetermined dividing ratio to output a sinusoidal wave clock signal;
a surge current preventing section for removing a surge current of the sinusoidal wave clock signal;
a square wave converting section for converting the sinusoidal wave clock signal having the surge current removed therefrom into a square wave clock signal using a driving power having no alternating current components;
a power noise removing section for removing a power noise included in the square wave clock signal outputted from the square wave converting section; and
a clock signal error correcting section for receiving the square wave clock signal outputted from the power noise removing section and outputting the received square wave clock signal after a predetermined delay time.
9. The apparatus according to claim 8 , wherein the square wave converting section comprises,
a power stabilizing part for removing an alternating current component of voltage signal components received from a driving power and maintaining a rated voltage; and
a Schmitt trigger for converting the sinusoidal wave having the surge current removed therefrom into a square wave clock signal, wherein the Schmitt trigger is driven by the driving power having the alternating current component removed therefrom.
10. The apparatus according to claim 9 , wherein the power stabilizing part comprises,
a MOS transistor serving as a diode, whose gate and source is commonly applied with the driving power; and
a capacitor for removing the alternating current component of the driving power, wherein the capacitor has an end connected to a ground and the other end connected to a drain of the transistor.
11. The apparatus according to claim 8 , wherein the surge current preventing section comprises a capacitor having an end connected to a ground and the other end connected to an input terminal of the square wave converting section.
12. The apparatus according to claim 8 , wherein the power noise removing section comprises,
a BJT transistor serving as a diode, whose base and collector are commonly connected and emitter is connected to a ground; and
a capacitor having an end commonly connected to the collector of the BJT transistor and the other end connected to a ground and removing an alternating current component of the square wave clock signal outputted from the square wave converting section.
13. The apparatus according to claim 8 , wherein the clock signal error correcting section comprises,
a resistance having an end connected to an output terminal of the power noise removing section; and
a capacitor having an end connected to the other end of the resistance and the other end connected to a ground.
14. An apparatus for generating a clock signal in a mobile communication terminal, the apparatus comprising:
a clock signal generating section for outputting a sinusoidal wave clock signal having an extremely low oscillating frequency;
an oscillating section for outputting a sinusoidal wave having a medium oscillating frequency;
a divider for dividing an output of the oscillating section in a predetermined dividing ratio to output a second sinusoidal wave clock signal;
a surge current preventing section for removing surge currents of the first and second clock signals;
a square wave converting section for converting the first and second sinusoidal wave clock signals having the surge currents removed therefrom into a square wave clock signal using a driving power having no alternating current components;
a power noise removing section for removing a power noise included in the square wave clock signal outputted from the square wave converting section; and
a clock signal error correcting section for receiving the square wave clock signals outputted from the power noise removing section and outputting the received square wave clock signals after a predetermined delay time.
15. The apparatus according to claim 14 , wherein the clock signal generating section comprises,
a crystal oscillating part for outputting a sinusoidal wave using a crystal oscillator;
an amplifying part for amplifying the sinusoidal wave outputted from the crystal oscillating part to a predetermined level; and
an automatic gain control for controlling a gain of the sinusoidal wave outputted from the amplifying part.
16. The apparatus according to claim 14 , wherein the square wave converting section comprises,
a power stabilizing part for removing an alternating current component of voltage signal components received from a driving power and maintaining a rated voltage; and
a Schmitt trigger for converting the sinusoidal wave having the surge current removed therefrom into a square wave clock signal, wherein the Schmitt trigger is driven by the driving power having the alternating current component removed therefrom.
17. The apparatus according to claim 16 , wherein the power stabilizing part comprises,
a MOS transistor serving as a diode, whose gate and source is commonly applied with the driving power; and
a capacitor for removing the alternating current component of the driving power, wherein the capacitor has an end connected to a ground and the other end connected to a drain of the transistor.
18. The apparatus according to claim 14 , wherein the surge current preventing section comprises a capacitor having an end connected to a ground and the other end connected to an input terminal of the square wave converting section.
19. The apparatus according to claim 14 , wherein the power noise removing section comprises,
a BJT transistor serving as a diode, whose base and collector are commonly connected and emitter is connected to a ground; and
a capacitor having an end commonly connected to the collector of the BJT transistor and the other end connected to a ground and removing an alternating current component of the square wave clock signal outputted from the square wave converting section.
20. The apparatus according to claim 14 , wherein the clock signal error correcting section comprises,
a resistance having an end connected to an output terminal of the power noise removing section; and
a capacitor having an end connected to the other end of the resistance and the other end connected to a ground.