IP Library Granted Patent US 7,650,471
Granted Patent B2
US 7,650,471 · App. 11/326,919 · Granted Jan 19, 2010

Head of queue cache for communication interfaces

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Quick Facts
Patent No.
US 7,650,471
App. No.
11/326,919
Granted
Jan 19, 2010
Kind
B2
Abstract

A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Claims (51)

1. A method comprising:

identifying an address of a head end of a queue;

monitoring a coherent interconnect to identify a data transfer communicated by a producer which targets the address;

storing data of the data transfer in the queue;

based at least in part on whether the monitoring identifies the address, selectively storing at least a portion of the data in a head-of-queue cache memory; and

selectively retrieving said at least a portion of the data from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

2. The method of claim 1 , wherein said queue is a circular queue having a head pointer, which points to the location of an oldest message in said queue, and a tail pointer, which points to a newest message in said queue.

3. The method of claim 2 , further comprising:

maintaining a table that stores the address; and

using the table to identify the data transfer that targets the head end of queue address.

4. The method of claim 3 , wherein the act of using the table comprises:

snooping on the coherent interconnect to identify the data transfer that targets the address.

5. The method of claim 1 , wherein said producer and said consumer are one of a virtual network interface circuit (VNIC) and a network interface controller (NIC).

6. The method of claim 5 , wherein said head-of-queue cache memory has an entry for each of a plurality of VNICs.

7. The method of claim 1 , wherein the act of storing said at least a portion of the data in the head-of-queue cache memory comprises:

prefetching said at least a portion of the data based on an updated head pointer.

8. The method of claim 1 , wherein the act of retrieving said data from said head-of-queue cache memory for transmission to said consumer further comprises:

determining if a message requested by said producer for transmission is present as part of said cached data;

if so, providing said cached data to a transmitter associated with said producer; and

otherwise, requesting said message from a main memory.

9. The method of claim 1 , wherein said producer comprises a graphics display list generator that generates a display list and said consumer comprises a display-list rendering engine.

10. The method of claim 1 , wherein the act of storing the data comprises the step of:

adding a terminating message at a tail of said queue.

11. The method of claim 10 , wherein the act of adding a terminating message at a tail of said queue comprises:

writing new data to said queue after a previously stored terminating message;

adding said terminating message after said new data; and

overwriting said previously stored terminating message to allow access to said new data.

12. A system for communicating data comprising:

a first device which is a producer of data;

a second device which is a consumer of said data;

a queue to store said data to be transmitted from said producer to said consumer, the queue having a head end of queue address;

a head-of-queue cache memory; and

a controller to monitor data transfers over a coherent interconnect to identify a data transfer that targets the head end of queue address and selectively store at least a portion of data from the identified data transfer in the head-of-queue cache memory.

13. The system of claim 12 , wherein said queue is a circular queue having a head pointer, which points to the location of an oldest message in said queue, and a tail pointer, which points to a newest message in said queue.

14. The system of claim 13 , further comprising:

a table to store an indication of the head end of queue address; and

a subsystem to maintain updates of the indication.

15. The system of claim 14 , wherein the controller comprises:

a snoop interface to monitor the coherent interconnect to identify the data transfer that targets the head end of queue address.

16. The system of claim 14 , further comprising:

a head offset table for tracking changes to head pointer locations as messages are added to or removed from said queue; and

an address translation lookup function for translating said changes into new physical head pointer addresses and updating said physical head pointer table.

17. The system of claim 12 , wherein said first device comprises a network interface controller (NIC) that presents a message address to a cache interface unit which either retrieves data associated with said message address from said head-of-queue cache or retrieves said data from a main memory unit via said coherent interconnect.

18. The system of claim 12 , wherein said first device comprises a graphics display list generator that generates a display list and said consumer device is a display-list rendering engine.

19. The system of claim 12 , wherein said data stored in said queue includes a terminating message at a tail of said queue.

20. A system for communicating data between a producer and a consumer comprising:

means for identifying an address of a head end of a queue;

means for monitoring a coherent interconnect to identify a data transfer communicated by a producer which targets the address;

means for storing data of the data transfer in the queue;

means for selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the head end of queue address; and

means for selectively retrieving said at least a portion of the data from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2006
From: SCHLANSKER, MICHAEL STEVEN; OERTLI, ERWIN; COLLARD, JEAN-FRANCOIS
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 017462/0717 →