Method for fabricating a MESFET
View Patent ↗A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in the substrate.
1. A method for fabricating a Metal-Semiconductor-Field-Effect-Transistor (MESFET), the method comprising:
forming an n-type channel portion in a substrate having a single n-doped channel region formed using a single implantation step; and
forming a p-type channel portion in the substrate, a boundary of the n-type channel portion and a boundary of the p-type channel portion defining an intrinsic region in the substrate.
2. A method in accordance with claim 1 further comprising forming at least one contact region in the substrate adjacent the intrinsic region and wherein the intrinsic region is between a side boundary of the p-type channel portion, a side boundary of the at least one contact region and a bottom boundary of the n-type channel portion.
3. A method in accordance with claim 2 wherein the at least one contact region comprises an n+ drain contact implant.
4. A method in accordance with claim 1 wherein forming the n-type channel portion comprises masking an n-type implant.
5. A method in accordance with claim 1 wherein forming the p-type channel portion comprises selectively and separately masking a p-type co-implant separate from an n-type implant forming the n-type channel portion above the p-type channel.
6. A method in accordance with claim 1 wherein forming the n-type channel portion and forming the p-type channel portion comprises using a photoresist mask to define regions for implanting the n-type channel portion and the p-type channel portion.
7. A method in accordance with claim 1 wherein the substrate comprises gallium arsenide (GaAs).
8. A method in accordance with claim 1 wherein the intrinsic region comprises a burnout improvement (BII) region configured as a compensating implant to prevent a p-n + junction from forming in a drain region.
9. A method in accordance with claim 1 wherein the n-type channel portion defines a main channel and the p-type channel portion defines a smaller channel.
10. A method for fabricating a Metal-Semiconductor-Field-Effect-Transistor (MESFET), the method comprising:
masking an n-type implant in a substrate to form an n-type channel region using a single implantation step;
masking a p-type co-implant in the substrate separate from the masking of the n-type implant to form a p-type channel region; and
masking a drain contact implant in the substrate to form a drain contact and wherein an intrinsic region is formed on one side by an entire side surface of the p-type co-implant, on another side by a side surface of the drain contact implant and on another side by a bottom surface of the n-type implant.
11. A method in accordance with claim 10 wherein masking the p-type co-implant comprises selectively masking the p-type co-implant.
12. A method in accordance with claim 10 wherein masking the p-type co-implant comprises photomasking.
13. A method in accordance with claim 10 wherein the intrinsic region comprises a burnout improvement region configured as a compensating n + -i-p burnout improvement region.
14. A method in accordance with claim 10 wherein the n-type channel region comprises a main channel portion.
15. A method in accordance with claim 10 further comprising passivizing a surface of the substrate above the n-type channel region.
16. A method in accordance with claim 10 wherein the n-type implant is masked before masking the p-type co-implant.
17. A method in accordance with claim 10 further comprising configuring the intrinsic region to reduce open channel burnout.