Method and apparatus for providing an integrated circuit having p and n doped gates

1. A method of forming a plurality of gate structures in an integrated circuit, the method comprising:

providing a substrate;

forming a first oxide layer on the substrate for a first plurality of gate structures to be located over a first area of the substrate;

conducting a first nitridation process to form a first nitrided oxide layer for at least a portion of the first oxide layer;

removing portions of the first oxide layer and first nitrided oxide layer over at least a second area of the substrate where a second plurality of gate structures are to be formed;

forming a second oxide layer on the substrate in at least the second area;

forming a conductive layer over the first nitrided oxide layer and the second oxide layer in the first and second areas in the first area;

in the first and second areas, doping a portion of the conductive layer to a first conductivity type;

in at least the first area, doping a portion of the conductive layer to a second conductivity type;

in at least one of the first and second areas, maintaining substantially no active dopant concentration in a portion of the conductive layer;

patterning the first oxide layer, the first nitrided oxide layer and the conductive layer to form a first plurality of gate stacks for a first plurality of devices; and

in the second area, patterning the second oxide layer and the conductive layer to form a second plurality of gate stacks for a second plurality of devices.

2. The method of claim 1 , further comprising the act of conducting a second nitridation process to include nitrogen in at least a portion of the second oxide layer.

3. The method of claim 2 , wherein the second oxide layer is formed having a nitrogen concentration less than that of the first nitrided oxide layer.

4. The method of claim 1 , wherein the second oxide layer is formed having substantially no nitrogen concentration

5. The method of claim 1 , wherein the first gate oxide layer is formed having a thickness between about 10 Å and about 30 Å.

6. The method of claim, 1 wherein the second oxide layer is formed having a thickness between about 20 Å and about 100 Å.

7. The method of claim 1 , wherein the first plurality of devices comprise peripheral circuitry of an image sensor array.

8. The method of claim 1 , wherein the first plurality of devices comprise digital and analog circuitry.

9. The method of claim 1 , wherein the second plurality of devices comprise an array of pixels.

10. The method of claim 1 , wherein the conductive layer is formed comprising polysilicon.

11. The method of claim 1 , wherein, in the first area, the devices comprise PMOS and NMOS devices.

12. The method of claim 1 , wherein the first and second pluralities of devices comprise transistors.

13. A method of forming an image sensor comprising:

providing a substrate;

forming a first oxide layer on the substrate;

conducting a nitridation process to form a first nitrided oxide layer from at least a portion of the first oxide layer;

removing portions of the first nitrided oxide layer and first oxide layer over a first area of the substrate;

forming a second oxide layer on the substrate in at least the first area;

forming a conductive layer over the first oxide layer, first nitrided oxide layer and the second oxide layer;

doping a portion of the conductive layer to a first conductivity type;

doping a portion of the conductive layer to a second conductivity type;

patterning the first oxide layer, first nitrided oxide layer and the conductive layer to form a first plurality of gate stacks for a first plurality of devices; and

patterning the second oxide layer and the conductive layer to form a second plurality of gate stacks for a second plurality of devices, forming the second plurality of devices comprising forming an array of pixels on the substrate, forming at least one pixel comprising:

forming a photo-conversion device, and

forming a first transistor coupled to the photo-conversion device, the first transistor having a gate stack comprising the second oxide layer and the conductive layer;

maintaining substantially no active dopant concentration in a portion of the conductive layer of the first transistor.

14. The method of claim 13 , wherein the first oxide layer is formed having a thickness between about 10 Å and about 30 Å.

15. The method of claim 13 , wherein the second oxide layer is formed having a thickness between about 20 Å and about 100 Å.

16. The method of claim 13 , further comprising:

forming a second transistor coupled to a floating diffusion region, the second transistor having a gate stack comprising the second oxide layer and the conductive layer;

doping a portion of the conductive layer of the second transistor to a second conductivity type and having an active dopant concentration of less than or equal to about 1×10 20 atoms/cm 3 .

17. The method of claim 16 , wherein the second oxide layer of the second transistor is formed having substantially no nitrogen concentration.

18. The method of claim 13 , wherein forming the second oxide layer comprises forming the second oxide layer having a nitrogen concentration less than that of the first nitrided oxide layer.

19. The method of claim 13 , wherein the second plurality of devices are formed within an array of pixels.

20. The method of claim 19 , wherein first plurality of devices are formed within circuitry peripheral to the array of pixels.

21. The method of claim 13 , wherein forming the second oxide layer comprises forming the second oxide layer having substantially no nitrogen concentration.

22. The method of claim 13 , further comprising, maintaining substantially no active dopant concentration in a portion of the conductive layer.

23. The method of claim 13 , wherein the conductive layer is formed comprising polysilicon.

24. The method of claim 13 , wherein the second oxide layer is formed having a greater thickness than a thickness of the first oxide layer.

25. The method of claim 13 , wherein the second oxide layer of the first transistor is formed having substantially no nitrogen concentration.