Memory having status register read function
A memory includes a status register and a read/write data bus. The status register is configured to pass status register values to the read/write data bus in response to a status register read command.
1 . A memory comprising:
a status register; and
a read/write data bus,
wherein the status register is configured to pass status register values to the read/write data bus in response to a status register read command.
2 . The memory of claim 1 , further comprising:
data read first-in first-out cells for latching the status register values from the read/write data bus.
3 . The memory of claim 1 , further comprising:
a data path configured to pass memory array data to the read/write data bus.
4 . The memory of claim 3 , further comprising:
a mode register block configured to activate a first control signal in response to the status register read command,
wherein the status register is configured to pass the status register values to the read/write data bus in response to the first control signal, and
wherein the data path is configured to block memory array data from passing to the read/write data bus in response to the first control signal.
5 . The memory of claim 4 , further comprising:
a burst length control block configured to provide a second control signal in response to a read command,
wherein the mode register block is configured to deactivate the first control signal in response to the second control signal.
6 . A memory comprising:
a mode register block configured to activate a first control signal in response to a status register read command;
a status register configured to pass status register values to a data bus in response to the first control signal; and
an array data path configured to block array data from passing to the data bus in response to the first control signal.
7 . The memory of claim 6 , further comprising:
a burst length control block configured to activate a second control signal in response to a read command,
wherein the mode register block is configured to deactivate the first control signal in response to the second control signal.
8 . The memory of claim 7 , wherein the burst length control block is configured to deactivate the second control signal based on a burst length signal.
9 . The memory of claim 7 , wherein the burst length control block is configured to deactivate the second control signal in response to a burst stop command.
10 . The memory of claim 7 , wherein the burst length control block is configured to deactivate the second control signal in response to a precharge command.
11 . The memory of claim 6 , wherein the memory comprises a dynamic random access memory.
12 . A dynamic random access memory comprising:
means for storing status data; and
means for passing the status data to output pads of the memory in response to a status data read command followed by a read command.
13 . The memory of claim 12 , further comprising:
means for exiting a status data read mode in response to a burst stop command.
14 . The memory of claim 12 , further comprising:
means for exiting a status data read mode in response to a precharge command.
15 . The memory of claim 12 , further comprising:
means for exiting a status data read mode based on a fixed burst length.
16 . The memory of claim 12 , further comprising:
means for blocking memory array data from passing to the output pads of the memory in response to the status data read command.
17 . A method for reading a status register in a memory, the method comprising:
receiving a status register read command;
passing status register values from a status register to a data bus in response to the status register read command;
receiving a read command; and
outputting the status register values on data pads of the memory in response to the read command.
18 . The method of claim 17 , further comprising:
blocking memory array data from passing to the data bus in response to the status register read command.
19 . The method of claim 17 , further comprising:
activating a status register control signal in response to the status register read command to pass the status register data from the status register to the data bus.
20 . The method of claim 17 , further comprising:
activating a pulse active read signal in response to the read command; and
delaying the pulse active read signal based on a latency,
wherein outputting the status register values comprises outputting the status register values in response to the delayed pulse active read signal.
21 . A method for reading a status register in a memory, the method comprising:
receiving a status register read command;
activating a first signal in response to the status register read command;
blocking memory array data from passing to a data bus in response to the first signal;
passing status register values from a status register to the data bus in response to the first signal;
latching the status register values from the data bus in data read latches;
receiving a read command;
activating a second signal in response to the read command; and
outputting the status register data from the data read latches in response to the second signal.
22 . The method of claim 21 , further comprising:
deactivating the first signal in response to the second signal.
23 . The method of claim 21 , further comprising:
deactivating the second signal based on a fixed burst length.
24 . The method of claim 21 , further comprising:
deactivating the second signal in response to a burst stop command.
25 . The method of claim 21 , further comprising:
deactivating the second signal in response to a precharge command.