Memory device comprising a memory layer and a metal chalcogenide ion-source layer
View Patent ↗A memory element in which data recording and data readout can be performed stably without difficulties and which can be manufactured with a comparatively simplified method is provided. The memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and the second electrode 6 , in which the ion source layer 3 contains any of elements selected from Cu, Ag, Zn and any of elements selected from Te, S, Se, and the ion source layer further contains boron (or rare-earth elements and silicon).
1. A memory element comprising:
a memory layer and an ion source layer positioned between first and second electrodes,
wherein the memory element is adapted to record data using a change in an electrical characteristic of the memory layer,
wherein the memory layer and the ion source layer are formed separately from each other,
wherein said ion source layer contains Cu, Ag, and Zn and one or more elements selected from Te, S, Se, and
wherein said ion source layer further comprises rare-earth elements, silicon and boron to maintain a uniform structure of the ion source layer after the memory element is subjected to a high-temperature heat treatment.
2. The memory element of claim 1 , wherein the electrical characteristic is electrical resistance.
3. The memory element of claim 1 , wherein the memory film is formed at a time the memory element is manufactured.
4. A memory device comprising:
a first memory element including a first memory layer and a first ion source layer positioned between first and second electrodes, a first wiring connected to a first side of the first electrode, wherein the first memory layer and the first ion source layer are formed separately from each other,
a second wiring connected to a second side of the second electrode,
a second memory element including a second memory layer and a second ion source layer positioned between third and fourth electrodes, wherein the second memory layer and the second ion source layer are formed separately from each other,
a third wiring connected to a third side of the third electrode,
a fourth wiring connected to a fourth side of the fourth electrode,
wherein:
each of the first and second ion source layers comprises Cu, Ag, and Zn and one or more elements selected from Te, S, Se,
each of the first and second ion source layers further comprises rare-earth elements, silicon and boron to maintain a uniform structure of each of the first and second ion source layers after the memory device is subjected to a high-temperature heat treatment,
the first memory element is adapted to record data using a change in an electrical characteristic of the first memory layer, and
the second memory element is adapted to record data using a change in an electrical characteristic of the second memory layer.
5. The memory device of claim 4 , wherein the electrical characteristic is electrical resistance.
6. The memory device of claim 4 , wherein the first and third wirings are electrically coupled.
7. A memory device comprising:
a first memory element including a first memory layer and a first ion source layer positioned between first and second electrodes, a first wiring connected to a first side of the first electrode, wherein the first memory layer and the first ion source layer are formed separately from each other,
a second wiring connected to a second side of the second electrode,
a second memory element including a second memory layer and a second ion source layer positioned between third and fourth electrodes, wherein the second memory layer and the second ion source layer are formed separately from each other,
a third wiring connected to a third side of the third electrode,
a fourth wiring connected to a fourth side of the fourth electrode,
wherein:
each of the first and second ion source layers comprises Cu, Ag, and Zn and one or more elements selected from Te, S, Se,
each of the first and second ion source layers further comprises boron to maintain a uniform structure of the ion source layer after the memory element is subjected to a high-temperature heat treatment,
the first memory element is adapted to record data using a change in an electrical characteristic of the first memory layer, and
the second memory element is adapted to record data using a change in an electrical characteristic of the second memory layer.
8. The memory device according to claim 7 ,
wherein the first ion source layer in the first memory element further comprises rare-earth elements or silicon and the second ion source layer in the second memory element further comprises rare-earth elements or silicon.
9. The memory device of claim 7 , wherein:
the electrical characteristic is electrical resistance.
10. The memory device of claim 7 , wherein the first and third wirings are electrically coupled.
11. A memory element comprising:
a memory layer and an ion source layer positioned between first and second electrodes,
wherein the memory element is adapted to record data using a change in an electrical characteristic of the memory layer,
wherein the memory layer and the ion source layer are formed separately from each other,
wherein said ion source layer comprises Cu, Ag, and Zn and one or more elements selected from Te, S, Se, and
wherein said ion source layer further comprises boron to maintain a uniform structure of the ion source layer after the memory element is subjected to a high-temperature heat treatment.
12. The memory element according to claim 11 ,
wherein said ion source layer comprises rare-earth elements or silicon.
13. The memory element of claim 11 , wherein the electrical characteristic is electrical resistance.
14. The memory element of claim 11 , wherein the memory layer is formed at a time the memory element is manufactured.
15. The memory element of claim 1 , wherein the memory layer has a thickness from 0.5 nm to 10 nm.
16. The memory element of claim 11 , wherein the memory layer includes at least one oxide of a rare-earth element.
17. The memory element of claim 11 , wherein Cu, Ag, and Zn form a current path or an impurity region in the memory layer when the data is recorded.
18. The memory element of claim 11 , wherein the memory layer has a high resistance.
19. The memory element of claim 11 , wherein the memory element has a thickness of 50 nm or less.
20. The memory element of claim 11 , wherein, when the boron is added, a uniform amorphous structure of the ion source layer is maintained after the memory element is subjected to the high-temperature heat treatment.