Information processing device, data transmission method, and electronic apparatus
View Patent ↗An information processing device in which a data bus for establishing interconnection between a plurality of control operating units formed in a main processor is connected at one end to a graphic processor and at the other end to a main memory. Image frame data generated by the graphic processor is sequentially transferred through the data bus and stored into the main memory. The data bus satisfies R 1 ≧R 2 ≧R 4 and R 1 ≧R 3 ≧R 4 , where R 1 is the data transmission rate from the main processor to the graphic processor, R 2 is the data transmission rate from the graphic processor to the main processor, R 3 is the data transmission rate between the main processor and the main memory, and R 4 is the rate to transmit a single image frame of data within a vertical blanking interval.
1. An information processing device comprising:
a main processor which exercises centralized control on the entire device, the main processor including a plurality of operating units;
a graphic processor which executes an image processing operation;
a main memory which stores data including image frame data which is generated by the graphic processor; and
a data bus used for internal data transmission from one of the plurality of operating units to the other operating units in the main processor, the data bus being directly, without any intervening elements, connected at one end to the graphic processor and at the other end to the main memory, wherein
the data bus is shared by the plurality of operating units for the internal data transmission in the main processor, and by the graphic processor and the main memory for the transmission of data including the image frame data therebetween, and
the image frame data is transmitted from the graphic processor to the main memory via the data bus and again transmitted via the bus in opposite direction to be directly output to an image display unit connected to the graphic processor according to a display timing.
2. The information processing device according to claim 1 , wherein the graphic processor has a direct memory access (DMA) controller which transfers generated image frame data to the main memory.
3. The information processing device according to claim 1 , wherein the data bus is configured to satisfy
R1≧R2 and R1≧R3,
where R 1 is a data transmission rate from the main processor to the graphic processor, R 2 is a data transmission rate from the graphic processor to the main processor, and R 3 is a data transmission rate between the main memory and the main processor.
4. The information processing device according to claim 1 , wherein the data bus is configured to satisfy
R1≧R4, R2≧R4, and R3≧R4,
where R 1 is a data transmission rate from the main processor to the graphic processor, R 2 is a data transmission rate from the graphic processor to the main processor, R 3 is a data transmission rate between the main memory and the main processor, and R 4 is a data transmission rate necessary to transmit image frame data from the information processing device to an image display unit connected to the information processing device so that the image frame data is displayed on the image display unit in real time.
5. The information processing device according to claim 1 , wherein:
the graphic processor has a graphic memory which stores image frame data; and
the graphic memory has a capacity smaller than or equal to the data size of two image frames.
6. The information processing device according to claim 1 , further comprising a display controller which reads pixel data out of the image frame data stored in the main memory line by line in succession and outputs the pixel data to the image display unit.
7. A data transmission method of an information processing device, the device comprising: a main processor which exercises centralized control on the entire device, the main processor including a plurality of operating units; a graphic processor which executes an image processing operation; a main memory which stores data including image frame data which is generated by the graphic processor; and a data bus used for internal data transmission from one of the plurality of operating units to the other operating units in the main processor, the data bus being directly, without any intervening elements, connected at one end to the graphic processor and at the other end to the main memory,
the method comprising performing transmission of data including the image frame data between the graphic processor and the main memory via the data bus shared with the plurality of operating units for the internal data transmission in the main processor, the image data being transmitted from the graphic processor to the main memory via the data bus, and again transmitted via the bus in opposite direction to be directly output to an image display unit connected to the graphic processor according to a display timing.
8. An electronic apparatus comprising:
the information processing device according to claim 1 ; and
an image display unit which outputs image frame data generated by the information processing device.