IP Library Granted Patent US 8,130,871
Granted Patent B2
US 8,130,871 · App. 11/328,830 · Granted Mar 6, 2012

Integrated circuit having radio receiver and methods for use therewith

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Quick Facts
Patent No.
US 8,130,871
App. No.
11/328,830
Granted
Mar 6, 2012
Kind
B2
Abstract

An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

Claims (49)

1. An integrated circuit comprising:

a radio receiver module to receive a radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and to convert a selected one of the plurality of channel signals into an output signal;

a channel selector module to produce a control signal;

a programmable decimation filter, responsive to the control signal, to down-sample the output signal to produce a down-sampled digital signal at a frequency that is a non-integer multiple of a carrier frequency of the selected one of the plurality of channel signals;

an interface clock generator, responsive to the control signal, to generate a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals wherein the first interface clock frequency, and integer multiples of the first interface clock frequency, are non-integer multiples of the carrier frequency of the selected one of the plurality of channel signals; and

a driver module, operably coupled to the interface clock generator, to drive a device interface to couple a device to the radio receiver module based on the first interface clock; wherein the device interface is a bidirectional interface that is configured to exchange control data between the radio receiver module and the device.

2. The integrated circuit of claim 1 wherein the driver module produces a device interface signal that is clocked at the first interface clock frequency.

3. The integrated circuit of claim 2 wherein the device interface signal includes an audio channel signal.

4. The integrated circuit of claim 1 wherein the driver module receives a device interface signal that is sampled at the first interface clock frequency.

5. The integrated circuit of claim 4 wherein the device interface signal includes control data.

6. The integrated circuit of claim 1 wherein the interface clock generator includes:

a controller module to produce a first divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

a first programmable divider module, operably coupled to the controller module, to produce the first interface clock by dividing a reference oscillation by the first divisor.

7. The integrated circuit of claim 6 wherein the first programmable divider module includes a fractional divider.

8. The integrated circuit of claim 6 wherein the controller module further produces a second divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals and wherein the interface clock generator further includes a second programmable divider module, operably coupled to the controller module, to produce a second interface clock by dividing the reference oscillation by the second divisor.

9. The integrated circuit of claim 1 wherein the interface clock generator includes:

a first divider module to produce the first interface clock by dividing a local oscillation signal by a first divisor.

10. The integrated circuit of claim 9 wherein the first divider module includes a fractional divider.

11. The integrated circuit of claim 9 wherein the interface clock generator includes:

a second divider module to produce a second interface clock by dividing the local oscillation signal by a second divisor.

12. The integrated circuit of claim 1 wherein the device interface is an integrated circuit device.

13. The integrated circuit of claim 1 wherein the first interface clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.

14. The integrated circuit of claim 1 wherein the received radio signal is one of a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

15. The integrated circuit of claim 1 wherein the radio receiver module includes an in-phase signal path and a quadrature-phase signal path.

16. A method comprising:

receiving, at a radio receiver module, a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies;

selecting a channel signal from the plurality of channel signals and producing a control signal based on a carrier frequency of the selected channel signal;

converting, using the radio receiver module, the selected one of the plurality of channel signals into an output signal;

down-sampling, in response to the control signal, the output signal to produce a down-sampled digital signal at a frequency that is a non-integer multiple of a carrier frequency of the selected channel signal;

generating a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals, wherein the first interface clock frequency, and each integer multiple of the first interface clock frequency, are non-integer multiples of the carrier frequency of the selected one of the plurality of channel signals; and

driving a device interface to couple a device to the radio receiver module based on the first interface clock, wherein the device interface is a bidirectional interface that is configured to exchange control data between the radio receiver module and the device.

17. The method of claim 16 wherein driving the device interface includes producing a device interface signal that is clocked at the first interface clock frequency.

18. The method of claim 17 wherein the device interface signal includes an audio channel signal.

19. The method of claim 16 wherein driving the device interface includes sampling a device interface signal at the first interface clock frequency.

20. The method of claim 19 wherein the device interface signal includes control data.

21. The method of claim 16 wherein generating the first interface clock includes:

producing a first divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

producing the first interface clock by dividing a reference oscillation by the first divisor.

22. The method of claim 21 wherein the first divisor includes a fraction.

23. The method of claim 21 wherein generating the first interface clock further includes:

producing a second divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

producing a second interface clock by dividing the reference oscillation by the second divisor.

24. The method of claim 16 wherein generating the first interface clock includes:

producing the first interface clock by dividing a local oscillation signal by a first divisor.

25. The method of claim 24 wherein the first divisor includes a fraction.

26. The method of claim 24 wherein generating the first interface clock further includes:

producing a second interface clock by dividing the local oscillation signal by a second divisor.

27. The method of claim 16 wherein the device interface is an integrated circuit device.

28. The method of claim 16 wherein the first interface clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: SIGMATEL, LLC
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037583/0428 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
CHANGE OF NAME Recorded Nov 23, 2015
From: SIGMATEL INC.
To: SIGMATEL, LLC
Reel/Frame 037152/0127 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →