Method of fabricating a thin film transistor using dual or multiple gates
View Patent ↗A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, θ angle in which “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined.
1. A method of fabricating a TFT using dual or multiple gates comprising:
calculating a probability including Nmax (the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels); and
adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, Θ angle in which the “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined,
wherein, the probability is a range from 0.75 to 1.
2. The method of claim 1 , wherein the probability is calculated as follows:
P =( D −( N max−1)× Gs )/ Gs
where D=L cos Θ+W sin Θ, L is the length of active channels of the TFT, W is the width of the active channels of the TFT, Nmax is the maximum number of “primary” crystal grain boundaries that can be contained in the active channel regions of a TFT having the length L and the width W, Gs is the size of crystal grains, Θ is an angle in which the “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the TFT, m is an integral number greater than 0, and W is the width of each active channel of the TFT having the dual or multiple gates.
3. The method of claim 1 , wherein the gap between the active channels is calculated as follows:
S=mGs· secΘ− L
where Gs is the size of crystal grains, Θ is an angle in which fatal crystal grain boundaries are inclined at a direction perpendicular to an active channel direction, and L is the length of each active of each of dual or multiple gates.
4. The method of claim 3 , wherein the angle is −45°≦Θ≦45°.
5. The method of claim 2 , wherein the gap between the active channels is calculated as follows:
S=mGs· secΘ− L
where Gs is the size of crystal grains, Θ is an angle in which fatal crystal grain boundaries are inclined at a direction perpendicular to an active channel direction, and L is the length of each active channel of each of dual or multiple gates.
6. The method of claim 5 , wherein the angle is −45°≦Θ≦45°.
7. A method of fabricating a TFT using dual or multiple gates comprising:
calculating a first probability in which N max, the maximum number of “primary” crystal grain boundaries capable of judging uniformity in TFT characteristics during fabrication of a TFT substrate using large silicon grains are included in active channel regions on the total substrate of a display device; and
using dual or multiple gates using the first probability to judge optimum process conditions on size and direction of silicon crystal grains and optimum dimensions of the active channels to secure uniformity of the TFT characteristics,
wherein, the first probability is a range from 0.75 to 1.
8. The method of claim 7 , wherein the probability is calculated as follows:
P =( D −( N max−1)× Gs )/ Gs
where D=L cos Θ+W sin Θ, L is the length of active channels of the TFT, W is the width of the active channels of the TFT; N max is the maximum number of “primary” crystal grain boundaries that can be contained in the active channel regions of a TFT having the length L and the width W, Gs is the size of crystal grains, Θ is an angle in which the “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the TFT, m is an integral number greater than 0, and L is the length of each active channel of the TFT having the dual or multiple gates.
9. The method of claim 7 , wherein the gap between the active channels is calculated as follows:
S=mGs· secΘ− L
where Gs is the size of crystal grains, Θ is an angle in which fatal crystal grain boundaries are inclined at a direction perpendicular to an active channel direction, and L is the length of each active of each of dual or multiple gates.
10. The method of claim 8 , wherein the angle is −45°≦Θ≦45°.
11. The method of claim 8 , wherein the gap between the active channels is calculated as follows:
S=mGs· secΘ− L
where Gs is the size of crystal grains, Θ is an angle in which fatal crystal grain boundaries are inclined at a direction perpendicular to an active channel direction, and L is the length of each active channel of each of dual or multiple gates.
12. The method of claim 11 , wherein the angle is −45°≦Θ≦45°.
13. The method of claim 1 , wherein the width of the active channels is 10 μm.
14. The method of claim 7 , wherein the width of the active channels is 10 um.