Thin film transistor and method of fabricating the same
View Patent ↗A thin film transistor and method of fabricating the same are provided. The thin film transistor is characterized in that low angle grain boundaries formed in a channel layer in a semiconductor layer pattern is tilted −15 to 15° with respect to a current flowing direction. The method includes: forming an amorphous silicon layer on a substrate; forming a first capping layer on the amorphous silicon layer; forming a second capping layer on the first capping layer, and patterning the second capping layer such that seeds are formed in a line shape; forming a metal catalyst layer on the patterned second capping layer; diffusing the metal catalyst; and crystallizing and patterning the amorphous silicon layer to form a semiconductor layer pattern. Thus, a channel layer having an angle nearly parallel to the current flowing direction may be formed in a low angle grain boundary by forming and crystallizing the line-shaped seeds. In other words, the device characteristics may be improved and uniformed by adjusting a position and a direction of the crystal growth.
1. A method of fabricating a thin film transistor, comprising:
forming an amorphous silicon layer on a substrate;
forming a capping layer on the amorphous silicon layer such that seeds are formed in a line shape, the capping layer comprising a metal catalyst diffusible portion and a metal catalyst non-diffusible portion;
forming a metal catalyst layer on the capping layer;
diffusing the metal catalyst through the capping layer; and
crystallizing and patterning the amorphous silicon layer to form a semiconductor layer pattern,
wherein the metal catalyst diffusible portion of the capping layer is part of a layer that is formed to cover an entire region of the amorphous silicon layer that includes the semiconductor layer pattern.
2. The method according to claim 1 , wherein the capping layer comprises at least two layers.
3. The method according to claim 2 , wherein the capping layer comprises:
a first capping layer on the amorphous silicon layer, and
a second capping layer pattern on the first capping layer.
4. The method according to claim 3 , wherein the second capping layer pattern is thicker than the first capping layer.
5. The method according to claim 3 , wherein the second capping layer pattern has a higher density than the first capping layer.
6. The method according to claim 3 , wherein an interval between the second capping layer patterns is 1 to 50 μm.
7. The method according to claim 2 , wherein the capping layer comprises:
a first capping layer pattern on the amorphous silicon layer, and
a second capping layer on the first capping layer pattern.
8. The method according to claim 7 , wherein the first capping layer pattern is thicker than the second capping layer.
9. The method according to claim 7 , wherein the first capping layer pattern has a higher density than the second capping layer.
10. The method according to claim 3 , wherein an interval between the first capping layer patterns is 1 to 50 μm.
11. The method according to claim 1 , wherein the capping layer comprises:
a capping layer on the amorphous silicon layer, the capping layer comprising a groove such that seeds are formed in a line shape.
12. The method according to claim 11 , wherein the groove formed in capping layers has a width of 1 to 50 μm.
13. The method according to claim 1 , wherein a distance between the line-shaped seeds is longer than a distance between the seeds in the line-shaped seeds.
14. The method according to claim 1 , wherein a channel layer in the semiconductor layer pattern is formed in between the line-shaped seeds and is spaced apart from the line-shaped seeds by at least ½ of a distance between the seeds of the line-shaped seeds.
15. The method according to claim 14 , wherein a difference of the distance between the line-shaped seeds and the distance between the seeds in the line-shaped seeds is larger than a length of the channel layer.
16. The method according to claim 1 , wherein the capping layer is made of any one of a silicon nitride layer and a silicon oxide layer.
17. The method according to claim 1 , wherein the capping layer is formed by a plasma enhanced chemical vapor deposition (PECVD) method.
18. A method of fabricating a thin film transistor, comprising:
forming an amorphous silicon layer on a substrate;
forming a capping layer on the amorphous silicon layer;
forming a metal catalyst layer on the capping layer;
diffusing the metal catalyst through the capping layer; and
crystallizing and patterning the amorphous silicon layer to form a semiconductor layer pattern,
wherein a distance between seeds in a parallel direction to a current flow direction in the semiconductor layer pattern is longer than a distance between seeds in a perpendicular direction to the current flow direction in the semiconductor layer pattern.
19. The method according to claim 18 , wherein the capping layer comprises at least two layers.
20. The method according to claim 19 , wherein the capping layer comprises:
a first capping layer on the amorphous silicon layer, and
a second capping layer pattern on the first capping layer, the second capping layer being patterned such that seeds are formed in a line shape.
21. The method according to claim 19 , wherein the capping layer comprises:
a first capping layer pattern on the amorphous silicon layer, the first capping layer being patterned such that seeds are formed in a line shape, and
a second capping layer on the first capping layer pattern.
22. The method according to claim 18 , wherein the capping layer comprises:
a capping layer on the amorphous silicon layer, and forming a groove in the capping layer such that seeds are formed in a line shape.
23. The method according to claim 18 , wherein the seeds are formed as a line-shaped.
24. The method according to claim 23 , wherein a channel layer in the semiconductor layer pattern is formed in between the line-shaped seeds and is spaced apart from the line-shaped seeds by at least ½ of a distance between the seeds of the line-shaped seeds.
25. The method according to claim 24 , wherein a difference of the distance between the line-shaped seeds and the distance between the seeds in the line-shaped seeds is larger than a length of the channel layer.