IP Library Granted Patent US 7,300,851
Granted Patent B2
US 7,300,851 · App. 11/331,258 · Granted Nov 27, 2007

Method of fabricating a silicon-on-insulator device with a channel stop

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Quick Facts
Patent No.
US 7,300,851
App. No.
11/331,258
Granted
Nov 27, 2007
Kind
B2
Abstract

A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Claims (11)

1. A method of forming a silicon-on-insulator device, comprising:

defining an active region in a silicon-on-insulator substrate;

doping the entire active region a first time with phosphorus;

masking a main part of the active region; and

doping peripheral parts of the active region at least a second time and a third time with phosphorus or antimony at different projection ranges,

wherein the impurity used is phosphorus the second time and antimony the third time or antimony the second time and phosphorus the third time.

2. The method of claim 1 , wherein the peripheral parts of the active region are doped the second and third times by ion implantation.

3. The method of claim 2 , wherein mutually different ion implantation energies are used the second time and the third time.

4. The method of claim 2 , wherein the peripheral parts of the active region are doped by ion implantation a fourth time in addition to the second time and the third time, mutually different ion implantation energies being used the second, third, and fourth times.

5. The method of claim 1 , wherein the silicon-on-insulator substrate is of the fully depleted type.

6. The method of claim 1 , wherein defining the active region comprises local oxidation of silicon.

Assignments (2)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Dec 24, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022052/0797 →