Structures and methods for fabricating vertically integrated HBT-FET device
View Patent ↗Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
1. A method of fabricating an epitaxial structure for fabricating an integrated pair of GaAs-based HBT and FET, said method comprising the steps of:
growing a first set of epitaxial layers, the first set of epitaxial layers forming a portion of the FET on a semi-insulating GaAs substrate;
growing a highly doped thick GaAs layer serving as a cap layer for the FET and a subcollector layer for the HBT;
growing a second set of epitaxial layers on the thick GaAs layer, the second set of epitaxial layers forming a portion of the HBT, and
forming an etch stop layer between the first set of epitaxial layers and the thick GaAs layer.
2. The method of claim 1 further comprising the step of isolating the HBT from the FET.
3. A method of fabricating an integrated heterojunction bipolar transistor (HBT) and a field effect transistor (FET) on a substrate comprising the steps of:
forming a first epitaxial structure on the substrate;
forming a second epitaxial structure on the first epitaxial structure;
forming a third epitaxial structure on the second epitaxial structure;
forming an etch stop layer between at least one of a) the first epitaxial structure and the second epitaxial structure and b) the second epitaxial structure and the third epitaxial structure;
forming the HBT from the third epitaxial structure;
forming an isolation barrier in the first and second epitaxial structures; and
forming the FET from the first and second epitaxial structures in a portion of the first and second epitaxial structures isolated from the HBT by the isolation barrier.
4. The method of claim 3 , wherein the step of forming an isolation barrier further comprises the step of implanting ions into the first and the second epitaxial structures between the HBT and the FET.
5. The method of claim 3 , further comprising the step of depositing a passivation layer on the HBT before forming the isolation barrier.
6. The method of claim 3 wherein an etch stop layer is formed between the first epitaxial structure and the second epitaxial structure, said method further comprising removing portions of the second epitaxial structure down to the etch stop layer.
7. The method of claim 3 wherein a first etch stop layer is formed between the first epitaxial structure and the second epitaxial structure and a second etch stop layer is formed between the second epitaxial structure and the third epitaxial structure.
8. The method of claim 7 wherein an etch-stop layer is formed between the second epitaxial structure and the third epitaxial structure, said method further comprising removing portions of the third epitaxial structure down to the etch stop layer.
9. The method of claim 3 wherein forming the first epitaxial structure comprises forming a MESFET epitaxial structure.
10. The method of claim 3 wherein forming the first epitaxial structure comprises forming a low leakage buffer layer on the substrate, forming an undoped spacer layer on the low leakage buffer layer and forming a doped channel layer on the undoped spacer layer.
11. The method of claim 3 wherein forming the first epitaxial structure comprises forming a pHEMT epitaxial structure.
12. The method of claim 3 wherein forming the first epitaxial structure comprises forming a lower barrier layer, forming a channel layer on the lower barrier layer and forming a Schottky barrier layer on the channel layer.
13. A method of fabricating an integrated heterojunction bipolar transistor (HBT) and a field effect transistor (FET) on a substrate comprising the steps of:
forming a first epitaxial structure on the substrate;
forming a second epitaxial structure on the first epitaxial structure
forming a third epitaxial structure on the second epitaxial structure;
forming an etch stop layer between at least one of a) the first epitaxial structure and the second epitaxial structure and b) the second epitaxial structure and the third epitaxial structure;
forming the HBT from the third epitaxial structure; and
forming the FET from the first and second epitaxial structures.
14. The method of claim 13 wherein an etch stop layer is formed between the second epitaxial structure and the third epitaxial structure, said method further comprising the step of removing portions of the third epitaxial structure down to the etch stop layer.
15. The method of claim 13 wherein a first etch stop layer is formed between the first epitaxial structure and the second epitaxial structure and a second etch stop layer is formed between the second epitaxial structure and the third epitaxial structure.
16. The method of claim 13 wherein an etch stop layer is formed between the first epitaxial structure and the second epitaxial structure, said method further comprising removing portions of the second epitaxial structure down to the etch stop layer.
17. The method of claim 13 wherein forming the first epitaxial structure comprises forming a MESFET epitaxial structure.
18. The method of claim 13 wherein forming the first epitaxial structure comprises forming a low leakage buffer layer on the substrate, forming an undoped spacer layer on the buffer layer, and forming a doped channel layer on the undoped spacer layer.
19. The method of claim 13 wherein forming the first epitaxial structure comprises forming a pHEMT epitaxial structure.
20. The method of claim 13 wherein forming the first epitaxial structure comprises forming a lower barrier layer, forming a channel layer on the lower barrier layer and forming a Schottky barrier layer on the channel layer.