Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate;

forming a passivation layer on the source electrode and the drain electrode;

forming a photoresist film on the passivation layer;

selectively etching the passivation layer using the photoresist film as a mask;

forming a conductive film on the remaining portion of the photoresist film and a portion of the gate and the drain electrode; and

removing the photoresist film and the conductive film using a chemical mechanical polishing process to form a pixel electrode connected to the drain electrode.

2. The method of claim 1 , wherein the photoresist film is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area and the photoresist film has a position-dependent thickness.

3. The method of claim 2 , wherein the etching of a passivation layer comprises forming a remaining portion of the photoresist film corresponding to the light blocking area of the photo mask.

4. The method of claim 3 , wherein the sidewalls of the passivation layer and the remaining portion of the photoresist film have a positive taper shape.

5. The method of claim 4 , wherein a surface height of the pixel electrode formed on the remaining portion of the photoresist film is the same as a surface height of the remaining portion of the photoresist film.

6. The method of claim 2 , wherein the translucent area is formed on an area enclosed by the gate line and the data line, including a portion of the drain electrode.

7. The method of claim 6 , wherein the etching of a passivation layer comprises forming a first contact hole exposing an end portion of the data line.

8. The method of claim 7 , wherein the etching of a passivation layer further comprises forming a second contact hole exposing an end portion of the gate line by etching the passivation layer with the gate insulating layer.

9. The method of claim 8 , wherein the formation of a pixel electrode comprises forming first and second contact assistants connected to the end portion of the data line and the end portion of the gate line through the first and second contact holes, respectively.

10. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line including a gate electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming an ohmic contact layer on the semiconductor layer;

forming a data line and a drain electrode on the ohmic contact layer;

forming a passivation layer on the data line and the drain electrode;

forming a first photoresist film on the passivation layer;

etching the passivation layer using the first photoresist film as a mask;

forming a conductive film on the remaining portion of the first photoresist film, a portion of the gate and the drain electrode and a portion of the gate insulating layer; and

removing the first photoresist film and the conductive film using a chemical mechanical polishing process to form a pixel electrode connected to the drain electrode.

11. The method of claim 10 , wherein the first photoresist film is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area so that the first photoresist film has a position-dependent thickness.

12. The method of claim 11 , wherein the translucent area is formed on an area enclosed by the gate line and the data line, including a portion of the drain electrode.

13. The method of claim 11 , wherein the etching of a passivation layer comprises forming a remaining portion of the first photoresist film corresponding to the light blocking area of the photo mask.

14. The method of claim 13 , wherein the sidewalls of the passivation layer, the gate insulating layer and the remaining portion of the photoresist film have a positive taper shape.

15. The method of claim 9 , wherein a surface height of the pixel electrode formed on the remaining portion of the first photoresist film is the same as a surface height of the remaining portion of the first photoresist film.

16. The method of claim 10 , wherein the etching of a passivation layer comprises forming a first contact hole exposing an end portion of the data line.

17. The method of claim 16 , wherein the etching of a passivation layer further comprises forming a second contact hole exposing an end portion of the gate line by etching the passivation layer with the gate insulating layer.

18. The method of claim 17 , wherein the formation of a pixel electrode comprises forming first and second contact assistants connected to the end portion of the data line and the end portion of the gate line through the first and second contact holes, respectively.

19. The method of claim 10 , wherein the formation of the semiconductor layer and the formation of the data line and the drain electrode comprise:

depositing the gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, and a conductive layer in sequence;

forming a second photoresist film on the conductive layer, such that the second photoresist film has different thicknesses in accordance with positions of the conductive layer; and

selectively etching the conductive layer, the extrinsic a-Si layer, and the intrinsic a-Si layer using the second photoresist film as a mask to form the data line, the drain electrode, and the ohmic contact layer.

20. The method of claim 19 , wherein the second photoresist film is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area.