Skew reduction for generated clocks
View Patent ↗There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets and other related nets. A transformed circuit design may be produced from an initial circuit design and having a reduced number of secondary clocks and a reduced amount of clock skew.
1. A process for transforming an initial circuit design, the initial circuit design having at least one primary clock and an initial number of secondary clocks derived from the primary clocks, the secondary clocks comprising generated clocks, the initial circuit design further having a plurality of sequential elements clocked by the secondary clocks, and the initial circuit design having an initial amount of clock skew associated with clocking the sequential elements from the secondary clocks, the process comprising
producing a transformed circuit design from the initial circuit design having
a transformed number of secondary clocks, wherein the transformed number is less than the initial number
a transformed amount of clock skew, wherein the transformed amount is less than the initial amount
wherein producing a transformed circuit design further comprises
selecting one of the sequential elements, the selected sequential element having a clock input
identifying the generated clock connected to the clock input of the selected sequential element
extracting the cone of logic that produces the generated clock
retiming forward the generated clock cone of logic
creating clock-enable logic for the selected generated clock
inserting the created clock-enable logic into the transformed circuit design
connecting the clock-enable logic to the selected sequential element
re-clocking the selected sequential element from the generated clock to the master clock.
2. The process for transforming an initial circuit design of claim 1 ,
wherein the secondary clocks further comprise gated clocks, and the initial circuit design includes a gating circuit having a gated clock net that drives a clock input of a selected sequential element, the selected sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net,
wherein producing a transformed circuit design further comprises
transforming the gating circuit to provide a second input net to the selected sequential element based on a cofactor condition of the gating circuit.
3. The process for transforming an initial circuit design of claim 2 , transforming comprising
obtaining an enable net
reconnecting the user-defined clock net and the first input net, wherein reconnecting comprises
disconnecting the gated clock net from clock input of the selected sequential element
connecting the user-defined clock net to the clock input of the selected sequential element
if the selected sequential element has an enable input, then combining the enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the enable net to the library enable input of the library element
removing the selected sequential element.
4. The process for transforming an initial circuit design of claim 1 , wherein at least some of the sequential elements have associated therewith respective polarities, the polarities selected from the group comprising rising-edge, falling-edge, active-high, active-low, the process comprising
modifying the polarity of at least one sequential element.
5. The process for transforming an initial circuit design of claim 1 , wherein the initial circuit design has original timing requirements, the process comprising
generating multi-cycle path constraints that reflect the original timing requirements.
6. The process for transforming an initial circuit design of claim 1 , wherein identifying the generated clock comprises
performing backward propagation from the clock input of the selected sequential element to a point where backward propagation does not reach a top-level port, whereby the clock connected at the point is identified as the generated clock.
7. The process for transforming an initial circuit design of claim 6 , wherein performing backward propagation includes
performing backward propagation across inverters and buffers.
8. The process for transforming an initial circuit design of claim 1 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
9. The process for transforming an initial circuit design of claim 8 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
10. The process of transforming an initial circuit design of claim 1 , wherein retiming forward the generated clock of logic comprises
retiming forward all sequential primary input of the generated cone of logic, across combinational logic.
11. The process for transforming an initial circuit design of claim 10 , further comprising
optionally replicate the retimed generated cone of logic for each sequential element connected to the generated clock
optionally generate identical routing topology for each replicated generated clock net
aborting any further processing when the retiming process does not entirely reduce the generated clock cone of logic to a single sequential element.
12. The process for transforming an initial circuit design of claim 1 , wherein creating the clock-enable logic comprises
generating the rising-edge clock-enable signal by inserting combinatorial gate logic that performs NOT (output of the retimed generated clock sequential element) AND (input of the retimed generated clock sequential element)
generating the falling-edge clock-enable signal by inserting combinatorial gate logic that performs (output of the retimed generated clock sequential element) AND NOT (input of the retimed generated clock sequential element).
13. The process for transforming an initial circuit design of claim 1 , wherein connecting the clock-enable logic to the selected sequential element comprises
if the selected sequential element has an enable input, then combining the clock enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the clock enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the clock enable net to the library enable input of the library element
removing the selected sequential element.
14. The process of transforming an initial circuit design of claim 1 , wherein re-clocking the selected sequential element from the generated clock to the master clock comprises
disconnecting the generated clock net from the clock input of the selected sequential element
connecting the master clock net to the clock input of the selected sequential element.
15. The process for transforming an initial circuit design of claim 14 , further comprising
when the selected sequential element is edge-triggered, changing its polarity to match the polarity of the retimed generated clock sequential element
when the selected sequential element is level-sensitive, changing its polarity to match the opposite polarity of the retimed generated clock sequential element.
16. The process for transforming an initial circuit design of claim 1 , further comprising
generating multi-cycle paths or virtual clocks so as to maintain the original timing requirements
modifying user multi-cycle paths so as to maintain the original timing requirements
forward annotating the multi-cycle paths or virtual clocks in the transformed circuit design for downstream implementation tools.
17. The process for transforming an initial circuit design of claim 1 , wherein the secondary clocks comprise gated clocks, the process comprising, prior to performing the steps of claim 6 , converting gated clocks to reduce the number of secondary clocks and to reduce clock skew.
18. A storage medium having instructions stored thereon which when executed by a processor will cause the processor to transform an initial circuit design, the initial circuit design having at least one primary clock and an initial number of secondary clocks derived from the primary clocks, the secondary clocks comprising generated clocks, the initial circuit design further having a plurality of sequential elements clocked by the secondary clocks, and the initial circuit design having an initial amount of clock skew associated with clocking the sequential elements from the secondary clocks, the process comprising
producing a transformed circuit design from the initial circuit design having
a transformed number of secondary clocks, wherein the transformed number is less than the initial number
a transformed amount of clock skew, wherein the transformed amount is less than the initial amount
wherein producing a transformed circuit design comprises
selecting one of the sequential elements, the selected sequential element having a clock input
identifying the generated clock connected to the clock input of the selected sequential element
extracting the cone of logic that produces the generated clock
retiming forward the generated clock cone of logic
creating clock-enable logic for the selected generated clock
inserting the created clock-enable logic into the transformed circuit design
connecting the clock-enable logic to the selected sequential element
re-clocking the selected sequential element from the generated clock to the master clock.
19. The storage medium for transforming an initial circuit design of claim 18 ,
wherein the secondary clocks further comprise gated clocks, and the initial circuit design includes a gating circuit having a gated clock net that drives a clock input of a selected sequential element, the selected sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net,
wherein producing a transformed circuit design further comprises
transforming the gating circuit to provide a second input net to the selected sequential element based on a cofactor condition of the gating circuit.
20. The storage medium for transforming an initial circuit design of claim 19 , transforming comprising
obtaining an enable net
reconnecting the user-defined clock net and the first input net, wherein reconnecting comprises
disconnecting the gated clock net from clock input of the selected sequential element
connecting the user-defined clock net to the clock input of the selected sequential element
if the selected sequential element has an enable input, then combining the enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the enable net to the library enable input of the library element
removing the selected sequential element.
21. The storage medium for transforming an initial circuit design of claim 18 , wherein at least some of the sequential elements have associated therewith respective polarities, the polarities selected from the group comprising rising-edge, falling-edge, active-high, active-low, the process comprising
modifying the polarity of at least one sequential element.
22. The storage medium for transforming an initial circuit design of claim 18 , wherein the initial circuit design has original timing requirements, the process comprising
generating multi-cycle path constraints that reflect the original timing requirements.
23. The storage medium for transforming an initial circuit design of claim 18 , wherein identifying the generated clock comprises
performing backward propagation from the clock input of the selected sequential element to a point where backward propagation does not reach a top-level port, whereby the clock connected at the point is identified as the generated clock.
24. The storage medium for transforming an initial circuit design of claim 23 , wherein performing backward propagation includes
performing backward propagation across inverters and buffers.
25. The storage medium for transforming an initial circuit design of claim 18 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
26. The storage medium for transforming an initial circuit design of claim 25 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
27. The storage medium of transforming an initial circuit design of claim 18 , wherein retiming forward the generated clock of logic comprises
retiming forward all sequential primary input of the generated cone of logic, across combinational logic.
28. The storage medium for transforming an initial circuit design of claim 27 , further comprising
optionally replicate the retimed generated cone of logic for each sequential element connected to the generated clock
optionally generate identical routing topology for each replicated generated clock net
aborting any further processing when the retiming process does not entirely reduce the generated clock cone of logic to a single sequential element.
29. The storage medium for transforming an initial circuit design of claim 18 , wherein creating the clock-enable logic comprises
generating the rising-edge clock-enable signal by inserting combinatorial gate logic that performs NOT (output of the retimed generated clock sequential element) AND (input of the retimed generated clock sequential element)
generating the falling-edge clock-enable signal by inserting combinatorial gate logic that performs (output of the retimed generated clock sequential element) AND NOT (input of the retimed generated clock sequential element).
30. The storage medium for transforming an initial circuit design of claim 18 , wherein connecting the clock-enable logic to the selected sequential element comprises
if the selected sequential element has an enable input, then combining the clock enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the clock enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the clock enable net to the library enable input of the library element
removing the selected sequential element.
31. The storage medium of transforming an initial circuit design of claim 18 , wherein re-clocking the selected sequential element from the generated clock to the master clock comprises
disconnecting the generated clock net from the clock input of the selected sequential element
connecting the master clock net to the clock input of the selected sequential element.
32. The storage medium for transforming an initial circuit design of claim 31 , further comprising
when the selected sequential element is edge-triggered, changing its polarity to match the polarity of the retimed generated clock sequential element
when the selected sequential element is level-sensitive, changing its polarity to match the opposite polarity of the retimed generated clock sequential element.
33. The storage medium for transforming an initial circuit design of claim 18 , further comprising
generating multi-cycle paths or virtual clocks so as to maintain the original timing requirements
modifying user multi-cycle paths so as to maintain the original timing requirements
forward annotating the multi-cycle paths or virtual clocks in the transformed circuit design for downstream implementation tools.
34. The storage medium for transforming an initial circuit design of claim 18 , wherein the secondary clocks comprise gated clocks, the process comprising, prior to performing the steps of claim 24 , convening gated clocks to reduce the number of secondary clocks and to reduce clock skew.
35. A computing system for transforming an initial circuit design, the computing device comprising:
a processor
a memory coupled with the processor
a storage medium having instructions stored thereon which when executed cause the computing device to transform can initial circuit design, the initial circuit design having at least one primary clock and an initial number of secondary clocks derived from the primary clocks, the secondary clocks comprising generated clocks, the initial circuit design further having a plurality of sequential elements clocked by the secondary clocks, and the initial circuit design having an initial amount of clock skew associated with clocking the sequential elements from the secondary clocks, the process comprising
producing a transformed circuit design from the initial circuit design having
a transformed number of secondary clocks, wherein the transformed number is less than the initial number
a transformed amount of clock skew, wherein the transformed amount is less than the initial amount
wherein producing a transformed circuit design comprises
selecting one of the sequential elements, the selected sequential element having a clock input
identifying the generated clock connected to the clock input of the selected sequential element
extracting the cone of logic that produces the generated clock
retiming forward the generated clock cone of logic
creating clock-enable logic for the selected generated clock
inserting the created clock-enable logic into the transformed circuit design
connecting the clock-enable logic to the selected sequential element
re-clocking the selected sequential element from the generated clock to the master clock.
36. The computing system for transforming an initial circuit design of claim 35 ,
wherein the secondary clocks further comprise gated clocks, and the initial circuit design includes a gating circuit having a gated clock net that drives a clock input of a selected sequential element, the selected sequential element receiving a first input net at a data input and generating an output net, the gating circuit having a user-defined clock net,
wherein producing a transformed circuit design comprises
transforming the gating circuit to provide a second input net to the selected sequential element based on a cofactor condition of the gating circuit.
37. The computing system for transforming an initial circuit design of claim 36 , transforming comprising
obtaining an enable net
reconnecting the user-defined clock net and the first input net, wherein reconnecting comprises
disconnecting the gated clock net from clock input of the selected sequential element
connecting the user-defined clock net to the clock input of the selected sequential element
if the selected sequential element has an enable input, then combining the enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the enable net to the library enable input of the library element
removing the selected sequential element.
38. The computing system for transforming an initial circuit design of claim 35 , wherein at least some of the sequential elements have associated therewith respective polarities, the polarities selected from the group comprising rising-edge, falling-edge, active-high, active-low, the process comprising
modifying the polarity of at least one sequential element.
39. The computing system for transforming an initial circuit design of claim 35 , wherein the initial circuit design has original timing requirements, the process comprising
generating multi-cycle path constraints that reflect the original timing requirements.
40. The computing system for transforming an initial circuit design of claim 35 , wherein identifying the generated clock comprises
performing backward propagation from the clock input of the selected sequential element to a point where backward propagation does not reach a top-level port, whereby the clock connected at the point is identified as the generated clock.
41. The computing system for transforming an initial circuit design of claim 40 , wherein performing backward propagation includes
performing backward propagation across inverters and buffers.
42. The computing system for transforming an initial circuit design of claim 35 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
43. The computing system for transforming an initial circuit design of claim 42 , wherein extracting the generated clock cone of logic comprises
performing a backward propagation from the clock pin of the selected sequential element, through combinational logic, to primary inputs.
44. The computing system of transforming an initial circuit design of claim 35 , wherein retiming forward the generated clock of logic comprises
retiming forward all sequential primary input of the generated cone of logic, across combinational logic.
45. The computing system for transforming an initial circuit design of claim 44 , further comprising
optionally replicate the retimed generated cone of logic for each sequential element connected to the generated clock
optionally generate identical routing topology for each replicated generated clock net
aborting any further processing when the retiming process does not entirely reduce the generated clock cone of logic to a single sequential element.
46. The computing system for transforming an initial circuit design of claim 35 , wherein creating the clock-enable logic comprises
generating the rising-edge clock-enable signal by inserting combinatorial gate logic that performs NOT (output of the retimed generated clock sequential element) AND (input of the retimed generated clock sequential element)
generating the falling-edge clock-enable signal by inserting combinatorial gate logic that performs (output of the retimed generated clock sequential element) AND NOT (input of the retimed generated clock sequential element).
47. The computing system for transforming an initial circuit design of claim 35 , wherein connecting the clock-enable logic to the selected sequential element comprises
if the selected sequential element has an enable input, then combining the clock enable net with an existing net connected to the enable input, the combined enable net and the existing net being connected to the enable input
if the selected sequential element does not have the clock enable input and there is a library element having a library enable input and functionally equivalent to the selected sequential element, then replacing the selected sequential element with the library element
reconnecting output pin and equivalent inputs of the selected sequential element to the library element
connecting the clock enable net to the library enable input of the library element
removing the selected sequential element.
48. The computing system of transforming an initial circuit design of claim 35 , wherein re-clocking the selected sequential element from the generated clock to the master clock comprises
disconnecting the generated clock net from the clock input of the selected sequential element
connecting the master clock net to the clock input of the selected sequential element.
49. The computing system for transforming an initial circuit design of claim 48 , further comprising
when the selected sequential element is edge-triggered, changing its polarity to match the polarity of the retimed generated clock sequential element
when the selected sequential element is level-sensitive, changing its polarity to match the opposite polarity of the retimed generated clock sequential element.
50. The computing system for transforming an initial circuit design of claim 35 , further comprising
generating multi-cycle paths or virtual clocks so as to maintain the original timing requirements
modifying user multi-cycle paths so as to maintain the original timing requirements
forward annotating the multi-cycle paths or virtual clocks in the transformed circuit design for downstream implementation tools.
51. The computing system for transforming an initial circuit design of claim 35 , wherein the secondary clocks comprise gated clocks, the process comprising, prior to performing the steps of claim 42 , converting gated clocks to reduce the number of secondary clocks and to reduce clock skew.