Apparatus and method for correcting IQ imbalance

1. A receiver for processing I and Q signals from a tuner, comprising:

a non-decision directed (NDD) imbalance canceller, coupled to receive the I and Q signals, configured to correct frequency-independent IQ imbalances and to converge independent of symbol decisions; and

a decision directed (DD) imbalance canceller, coupled to the NDD imbalance canceller, configured to correct frequency-dependent IQ imbalances and to converge based on symbol decisions after the NDD imbalance canceller converges, so as to correct IQ imbalances in the receiver.

2. The receiver of claim 1 , wherein the NDD imbalance canceller is configured to correct a majority of the IQ imbalances, and wherein the DD imbalance canceller is configured to correct a remainder of the IQ imbalances not previously corrected by the NDD imbalance canceller.

3. The receiver of claim 2 , wherein the IQ imbalances comprise:

frequency-dependent IQ imbalances and frequency-independent IQ imbalances.

4. The receiver of claim 3 , wherein the majority of the IQ imbalances comprises:

the frequency-independent IQ imbalances.

5. The receiver of claim 4 , wherein the frequency-independent IQ imbalances comprise:

gain IQ imbalances and phase IQ imbalances.

6. The receiver of claim 5 , wherein the phase IQ imbalances comprise:

sampling IQ imbalances.

7. The receiver of claim 3 , wherein the remainder of the IQ imbalances comprises:

frequency-dependent IQ imbalances.

8. The receiver of claim 7 , wherein the frequency-dependent IQ imbalances comprise:

filter IQ imbalances associated with filters in I and Q paths of the tuner.

9. The receiver of claim 1 , wherein the NDD imbalance canceller comprises:

an equalizer.

10. The receiver of claim 1 , wherein the DD imbalance canceller comprises:

an equalizer.

11. The receiver of claim 10 , wherein the equalizer comprises:

a feed-forward equalizer (FFE);

a decision feedback equalizer (DFE) coupled to the FFE;

an error generator circuit configured to generate an error signal, wherein the error generator circuit includes:

a first summer configured to combine outputs from the FFE and the DFE to generate a soft decision signal,

a slicer configured to process the soft decision signal to generate a hard decision signal, and

a second summer configured to combine the soft decision signal and the hard decision signal to generate the error signal; and

a coefficient update circuit that configured to update FFE and DFE filter coefficients based on the error signal.

12. The receiver of claim 11 , wherein the FFE and the DFE each comprise:

a plurality of finite impulse response filters.

13. The receiver of claim 11 , wherein the FFE and the DFE each comprise:

four finite impulse response filters.

14. The receiver of claim 1 , wherein the receiver is further configured to correct intersymbol interference.

15. A method for processing I and Q signals from a tuner, comprising:

(a) converging a non-decision directed (NDD) imbalance canceller independent of symbol decisions to correct a majority of IQ imbalances that include frequency-independent IQ imbalances; and

(b) subsequently converging a decision directed (DD) imbalance canceller based on symbol decisions to correct a remainder of IQ imbalances not corrected in step (a) that include frequency-dependent IQ imbalances.

16. The method of claim 15 , wherein the frequency-independent IQ imbalances comprise:

gain IQ imbalances and phase IQ imbalances.

17. The method of claim 16 , wherein the phase IQ imbalances comprise:

sampling IQ imbalances.

18. The method of claim 16 , wherein step (a) comprises:

(a)(i) correcting the gain IQ imbalances by subtracting a Q signal power from an I signal power and converging the difference; and

(a)(ii) correcting the phase IQ imbalances by multiplying the I signal by the Q signal and converging an expected value of the product.

19. The method of claim 15 , wherein the frequency-dependent IQ imbalances comprise:

filter IQ imbalances associated with filters in I and Q paths of the tuner.

20. The method of claim 15 , wherein step (b) comprises:

(b)(i) converging the DD imbalance canceller to correct intersymbol interference.

21. The method of claim 15 , wherein step (b) comprises:

(b)(i) converging the DD imbalance canceller in a constant modulus algorithm (CMA) mode; and

(b)(ii) subsequently converging the DD imbalance canceller in an asymmetric mode.

22. The method of claim 21 , wherein step (b)(ii) comprises:

(b)(ii)(A) generating a soft decision signal by combining outputs from a feed forward equalizer (FFE) and a decision feedback equalizer (DFE);

(b)(ii)(B) generating a hard decision signal by processing the soft decision signal in a slicer;

(b)(ii)(C) generating an error signal based on the soft decision signal and the hard decision signal; and

(b)(ii)(D) updating FFE and DFE filter coefficients based on the error signal.

23. The receiver of claim 1 , further comprising:

a summer configured to combine outputs from a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) to generate a soft decision signal, the DD imbalance canceller being configured to converge based on symbol decisions of the soft decision signal.

24. The method of claim 15 , further comprising:

(c) combining outputs from a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) to generate a soft decision signal, and wherein step (b) comprises:

(b)(i) subsequently converging the DD imbalance canceller based on symbol decisions of the soft decision signal to correct the remainder of IQ imbalances.