Method, circuit and systems for erasing one or more non-volatile memory cells
View Patent ↗The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.
1. A method of erasing one or more non-volatile memory (“NVM”) cells in an NVM array segment, said method comprising: applying to an NVM cells an erase pulse whose characteristic is at least partially based upon an updateable erase pulse parameter associated with the given array segment; and
wherein the updateable erase pulse parameter is substantially correlated to an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
2. A method of erasing one or more non-volatile memory (“NVM”) cells in an NVM array segment, said method comprising: applying to an NVM cell an erase pulse whose characteristic is at least partially based upon an updateable erase pulse parameter associated with the given array segment; and
wherein the updateable erase pulse parameter is substantially correlated with a voltage which is offset from and lower than an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
3. A circuit for erasing a non-volatile memory (“NVM”) cell comprising: an erase pulse source to produce an erase pulse whose characteristic is based upon an updateable erase parameter associated with the given array segment; and
wherein the updateable erase pulse parameter is substantially correlated with an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
4. The circuit according to claim 3 , wherein the updateable erase pulse parameter is substantially correlated with a voltage which is offset from and lower than an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
5. A data storage system comprising: a non-volatile memory (“NVM”) cell array and a circuit adapted to produce an erase pulse source to produce an erase pulse whose characteristic is based upon an updateable erase parameter associated with the given array segment; and
wherein the updateable erase pulse parameter is substantially correlated with an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
6. The data storage system according to claim 5 , wherein the updateable erase pulse parameter is substantially correlated with a voltage which is offset from and lower than an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
7. A method of fabricating a non-volatile memory (“NVM”) cell array, said method comprising the steps of:
fabricating a non-volatile memory (“NVM”) cell array;
fabricating a circuit adapted for erasing a non-volatile memory (“NVM”) cell comprising: an erase pulse source to produce an erase pulse whose characteristic is based upon an updateable erase parameter associated with the given array segment; and
wherein the updateable erase pulse parameter is substantially correlated with an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.
8. The method according to claim 6 , wherein the updateable erase pulse parameter is substantially correlated with a voltage which is offset from and lower than an erase pulse voltage at which a relatively slow erasing NVM cell in the array segment was induced to reach a threshold voltage associated with an erase state during a previous erase operation.