Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
View Patent ↗Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can be used repeatedly for multiple-stage switching network and/or hierarchically arranged switching networks.
1. A circuit layout in an integrated circuit, the circuit layout comprising:
n1 rows of switches, each row of the n1 rows of switches organized along a second dimension, wherein the switches of each row are organized along a first dimension;
a first set of conductors comprising i1 conductors organized in proximity along a plurality of tracks in the second dimension distributed over the n1 rows, wherein y number of the first set of conductors are connected to a corresponding y number of the switches in each of the n1 rows for y ranging between (i1−n1+1) to i1; and
a second set of conductors comprising i2 conductors organized in n1 sets of non-overlapping conductors, each of the n1 sets of non-overlapping conductors having approximately (i2/n1) number of the second set of conductors along the plurality of tracks in the second dimension distributed over a respective row of the n1 rows, wherein the approximately (i2/n1) number of the second set of conductors are connected to the y number of the switches of the respective row.
2. The circuit layout of claim 1 , further comprising (i1+i2) tracks in proximity along the second dimension, wherein the first and the second sets of conductors are laid out over the n1 rows along the (i1+i2) tracks.
3. The circuit layout of claim 1 , further comprising at most (i2/2) tracks of interconnections in proximity along the first dimension, wherein each set of the n1 sets of the approximately (i2/n1) number of the second set of conductors are re-aligned in proximity along the plurality of tracks in the second dimension over the n1 rows through the at most (i2/2) tracks.
4. The circuit layout of claim 3 , further comprising (i1+i2) tracks in proximity along the second dimension, wherein the first and the second sets of conductors are laid out over the n1 rows along the (i1+i2) tracks.
5. A method of laying out an integrated circuit, comprising:
providing n1 rows of switches in the circuit layout, each of the n1 rows of switches organized along a second dimension, wherein switches of each row of the n1 rows of switches are organized along a first dimension;
organizing a first set of conductors, comprising i1 conductors, in proximity along a plurality of tracks in the second dimension distributed over the n1 rows of switches, wherein y number of the first set of conductors are connected to a corresponding y number of the switches in each of the n1 rows for y ranging between (i1−n1+1) to i1; and
organizing a second set of conductors, comprising i2 conductors, in n1 sets of non-overlapping conductors, each of the n1 sets of non-overlapping conductors having approximately (i2/n1) number of the second set of conductors along the plurality of tracks in the second dimension distributed over a respective row of the n1 rows of switches, wherein the approximately (i2/n1) number of the second set of conductors are connected to the y number of the switches of the respective row.
6. The method as set forth in claim 5 , further comprising:
providing (i1+i2) tracks in proximity along the second dimension; and
distributing the first and the second sets of conductors over the n1 rows of switches along the (i1+i2) tracks.
7. The method as set forth in claim 5 , further comprising:
providing at most (i2/2) tracks of interconnections in proximity along the first dimension; and
re-aligning each set of the n1 sets of the approximately (i2/n1) number of second set of conductors in proximity along the plurality of tracks in the second dimension over the n1 rows of switches through the at most (i2/2) tracks.
8. The method as set forth in claim 7 , further comprising:
providing (i1+i2) tracks in proximity along the second dimension; and
distributing the first and the second sets of conductors over the n1 rows of switches along the (i1+i2) tracks.
9. An integrated circuit layout, comprising:
a first set of conductors comprising i1 number of conductors organized in n1 sets of non-overlapping second set of conductors, each of the n1 sets of the second set of conductors having approximately (i1/n1) number of the first set of conductors, wherein each of the n1 sets of the second set of conductors are laid out in at least i1 number of tracks in proximity along a second dimension; and
at most (i1/2) tracks along a first dimension, wherein each of the n1 sets of the second set of conductors are re-aligned in proximity along the second dimension through the at most (i1/2) tracks along the first dimension.
10. A method of laying out an integrated circuit, comprising:
organizing a first set of conductors, comprising i1 number of conductors, in n1 sets of non-overlapping second set of conductors, each of the n1 sets of the second set of conductors having approximately (i1/n1) number of the first set of conductors;
distributing in proximity each of the second set of conductors in at least i1 number of tracks along a second dimension of a circuit layout;
providing at most (i1/2) tracks along a first dimension of the integrated circuit; and
re-aligning in proximity each of the n1 sets of the second set of conductors along the second dimension in the circuit layout through the at most (i1/2) tracks along the first dimension.
11. An article of manufacture comprising a machine readable medium that stores data representing an integrated circuit layout, comprising:
n1 rows of switches, each row of the n1 rows of switches organized along a second dimension, wherein the switches of each row are organized along a first dimension;
a first set of conductors comprising i1 conductors organized in proximity along a plurality of tracks in the second dimension distributed over the n1 rows, wherein y number of the first set of conductors are connected to a corresponding y number of the switches in each of the n1 rows for y ranging between (i1−n1+1) to i1; and
a second set of conductors comprising i2 conductors organized in n1 sets of non-overlapping conductors, each of the n1 sets of non-overlapping conductors having approximately (i2/n1) number of the second set of conductors along the plurality of tracks in the second dimension distributed over a respective row of the n1 rows, wherein the approximately (i2/n1) number of the second set of conductors are connected to the y number of the switches of the respective row.
12. The article of manufacture of claim 11 , wherein the data representing the integrated circuit layout further comprises (i1+i2) tracks in proximity along the second dimension, wherein the first and the second sets of conductors are laid out over the n1 rows along the (i1+i2) tracks.
13. The article of manufacture of claim 11 , wherein the data representing the integrated circuit layout further comprises at most (i2/2) tracks of interconnections in proximity along the first dimension, wherein each set of the n1 sets of the approximately (i2/n1) number of the second set of conductors are re-aligned in proximity along the plurality of tracks in the second dimension over the n1 rows through the at most (i2/2) tracks.
14. The article of manufacture of claim 11 , wherein the data representing the integrated circuit layout further comprises (i1+i2) tracks in proximity along the second dimension, wherein the first and the second sets of conductors are laid out over the n1 rows along the (i1+i2) tracks.
15. An article of manufacture comprising a machine readable medium that stores data representing an integrated circuit layout, comprising:
a first set of conductors comprising i1 number of conductors organized in n1 sets of non-overlapping conductors, each of the n1 sets of non-overlapping conductors having approximately (i1/n1) number of the first set of conductors, wherein each of the approximately (i1/n1) number of the first set of conductors are laid out in at least i1 number of tracks in proximity along a second dimension; and
at most (i1/2) tracks along a first dimension, wherein each of the n1 sets of the first set of conductors are re-aligned in proximity along the second dimension through the at most (i1/2) tracks along the first dimension, each of the n1 sets of the first set of conductors having approximately (i1/n1) number of the second set of conductors.