Thin film transistor array panel and method of manufacturing the same
View Patent ↗The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
1. A method of manufacturing a TFT array panel comprising:
forming a plurality of thin film transistors each having a gate electrode, a source electrode, and a drain electrode;
forming an insulating layer on the thin film transistors;
forming a first conductive layer electrically connected to the drain electrodes on the insulating layer;
forming a second conductive layer on the first conductive layer;
forming a photoresist layer including first portions and second portions thinner than the first portions;
selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and
selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
2. The method of claim 1 , further comprising:
etching the photoresist layer to remove the second portions and to expose the second conductive layer after the selective etching of the first conductive layer; and
selectively etching the exposed portions of the second conductive layer with the first etchant by using the first portions of the photoresist layer as an etch blocker.
3. The method of claim 1 , wherein the first conductive layer contains ITO.
4. The method of claim 3 , wherein the ITO has an amorphous state.
5. The method of claim 4 , wherein the second etchant contains sulfuric acid.
6. The method of claim 4 , wherein the second etchant contains hydrochloric acid and a surfactant.
7. The method of claim 4 , wherein the second etchant contains oxalic acid and a surfactant.
8. The method of claim 3 , wherein the second conductive layer contains Al or an Al alloy.
9. The method of claim 8 , wherein the first etchant contains phosphoric acid, nitric acid, and acetic acid.
10. The method of claim 1 , wherein the formation of the first conductive layer is performed at a temperature between 25° C. and 150° C.
11. The method of claim 10 , wherein the formation of the first conductive layer is performed in an atmosphere of hydrogen gas (H 2 ) or water vapor (H 2 O).
12. A method of manufacturing a TFT array panel comprising:
forming a gate line;
forming a semiconductor, a data line and a drain electrode on the gate line;
forming a passivation layer and an organic insulating layer on the data line and the drain electrode;
sequentially depositing an amorphous ITO layer and a first conductive layer on the organic insulating layer;
forming a photoresist layer including first portions and second portions thinner than the first portions on the first conductive layer;
selectively etching the first conductive layer with a first etchant by using the photoresist layer as an etch blocker; and
selectively etching the amorphous ITO layer with a second etchant by using the photoresist layer and the first conductive layer as etch blockers;
etching the photoresist layer to remove the second portions and to expose the first conductive layer; and
selectively etching the exposed portions of the first conductive layer with the first etchant by using the first portions of the photoresist layer as an etch blocker.
13. The method of claim 12 , wherein the formation of the amorphous ITO layer is performed at a temperature between 25° C. and 150° C.
14. The method of claim 13 , wherein the formation of the amorphous ITO layer is performed in an atmosphere of hydrogen gas (H 2 ) or water vapor (H 2 O).
15. The method of claim 13 , wherein the second etchant contains sulfuric acid.
16. The method of claim 13 , wherein the second etchant contains hydrochloric acid and a surfactant.
17. The method of claim 13 , wherein the second etchant contains oxalic acid and a surfactant.
18. The method of claim 13 , wherein the first conductive layer contains Al or an Al alloy.
19. The method of claim 18 , wherein the first etchant contains phosphoric acid, nitric acid, and acetic acid.