Thin film transistor array panel and manufacturing method thereof

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

forming a first insulating layer on the gate line;

forming a semiconductor layer on the flint insulating layer;

forming a conductive layer;

forming a data line and a drain electrode from the conductive layer and on the semiconductor Layer;

depositing passivation layer on the data line and the drain electrode;

forming a photoresist on the passivation layer;

etching the passivation layer and the first insulating layer using the photoresist as a mask to expose portions of the conductive layer and at least a part of the substrate;

partially removing an exposed portion of the conductive layer;

depositing a conductive film on the photoresist, and exposed portions of the conductive layer and the substrate; and

removing the photoresist and the conductive film deposited on the photoresist, to form a pixel electrode connected to the exposed portion of the drain electrode.

2. The method of claim 1 , wherein the photoresist is formed by using a photo mask including a light blocking area and a light transmitting area.

3. The method of claim 1 , wherein the removing of the conductive layer comprises dry etching.

4. The method of claim 3 , wherein the removing of the conductive layer uses a Cl2/O2-containing gas.

5. The method of claim 1 , wherein the removing of the conductive layer comprises wet etching.

6. The method of claim 1 , wherein the exposed portion of the conductive layer has a length of at least 7.5 μm.

7. The method of claim 1 , wherein a distance between the gate line and the drain electrode is at least 6 μm.

8. The method of claim 1 , wherein the exposed portion of the conductive layer has an area range of 80 to 120 μm 2 .

9. The method of claim 1 , wherein the etching of the passivation layer and the first insulating layer generates an undercut region under the passivation layer and the first insulating layer.

10. The method of claim 1 , wherein forming the data line and the drain electrode comprises forming a storage capacitor conductor overlapping a portion of the gate line.

11. The method of claim 1 further comprising lifting off the conductive film formed on the photoresist.

12. The method of claim 1 , wherein the pixel electrode is at least partially connected to the substrate.

13. The method of claim 1 , wherein the etching of the passivation layer and the first insulating layer comprises:

forming a first contact hole exposing an end portion of the data line;

and

forming a first contact assistant connected to the end portion of the data line through the first contact hole.

14. The method of claim 13 , wherein the etching of the passivation layer and the first insulating layers comprises:

forming a second contact hole exposing an end portion of the gate line;

and

forming a second contact assistant connected to the end portion of the gate line through the second contact hole.

15. The method of claim 14 further comprising forming the pixel electrode along with the first and second contact assistants.

16. The method of claim 1 , wherein the semiconductor layer, the data line, and the drain electrode are formed in a single lithography step.