IP Library Granted Patent US 7,368,776
Granted Patent B2
US 7,368,776 · App. 11/336,966 · Granted May 6, 2008

Semiconductor device comprising a highly-reliable, constant capacitance capacitor

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Quick Facts
Patent No.
US 7,368,776
App. No.
11/336,966
Granted
May 6, 2008
Kind
B2
Abstract

A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.

Claims (29)

1. A semiconductor device comprising:

a semiconductor substrate having a major surface;

a field effect transistor formed on the major surface of said semiconductor substrate,

a conductor electrically connected to a source/drain region of said field effect transistor,

a cylindrical first electrode electrically connected to said conductor, and provided to upwardly extend beyond said conductor, and

a second electrode provided along an inner wall face of said cylindrical first electrode with a dielectric there between,

wherein a sidewall of said cylindrical first electrode includes a part in which a width between said sidewall is larger than the width between said sidewall at an upper end part of said cylindrical first electrode.

2. The semiconductor device according to claim 1 , wherein

said sidewall of said first electrode includes an upper part located at an upper end part of said cylindrical first electrode, and a lower part continuous to a lower side of said upper part, and

the width between said sidewall at said lower part is larger than the width between said sidewall at said upper part at a boundary region between said upper part and said lower part.

3. The semiconductor device according to claim 1 , wherein said sidewall of said cylindrical first electrode includes an upper part located at an upper end part of said cylindrical first electrode, and a lower part continuous to a lower side of said upper part,

an inner circumferential face is inclined with respect to the major surface of said semiconductor substrate such that, at a cross section of said cylindrical first electrode in a direction perpendicular to the major surface of said semiconductor substrate, a distance between the inner circumferential face of said lower part is greater than the distance between the inner circumferential face of said upper part, and the distance between said inner circumferential face increases from said upper part towards said lower part at a boundary region between said upper part and said lower part.

4. The semiconductor device according to claim 1 , wherein

said sidewall of said cylindrical first electrode includes an upper part located at an upper end part of said cylindrical first electrode, and a lower part continuous to a lower side of said upper part,

said sidewall of said cylindrical first electrode has a constriction at a boundary region between said upper part and said lower part,

a width between said sidewall at said lower part located below said constriction is larger than the width between said sidewall at an upper part located upper than said constriction.

5. The semiconductor device according to claim 1 , wherein said sidewall of said cylindrical first electrode has a curved face, and

said sidewall of said cylindrical first electrode includes an upper part located at an upper end part of said cylindrical first electrode, and a lower part continuous to a lower side of said upper part,

a width between said sidewall at said lower part is larger than the width between said sidewall at said upper part.

6. The semiconductor device according to claim 1 , further comprising granular crystals formed only on an inner side surface of said cylindrical first electrode.

7. A semiconductor device comprising:

a semiconductor substrate having a major surface,

first and second field effect transistors formed at the major surface of said semiconductor substrate,

first and second conductors electrically connected to a source/drain region of said first and second field effect transistors, respectively,

one set of cylindrical first electrodes electrically connected to said first and second conductors, respectively, and provided so as to upwardly extend beyond said first and second conductors, respectively, and

a second electrode provided along an inner wall face of said cylindrical first electrode with a dielectric there between,

a sidewall of said cylindrical first electrode including an upper part located at an upper end part of said cylindrical first electrode, and a lower part continuous to a lower side of said upper part,

a part of said cylindrical first electrode where a distance between the first electrodes of said one set is smallest is included in said lower part.

8. The semiconductor device according to claim 7 , comprising granular crystals formed only at an inner side surface of said cylindrical first electrode.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
CHANGE OF NAME Recorded Sep 10, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024973/0001 →