Thin film transistor array panel with enhanced storage capacitors
View Patent ↗A thin film transistor array panel is provided. The array panel includes a storage capacitance that is substantially uniform, and allows for a relatively large capacitance in a relatively small area. In some embodiments, the panel includes: a substrate; a plurality of semiconductor regions on the substrate, including a plurality of source and drain regions doped with a first impurity type and a dummy region doped with a second impurity type, and an intrinsic region having storage and channel regions; a gate insulating layer covering at least a portion of the semiconductor regions; a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer; a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer; a data line including a source electrode connected to the source region and formed on the gate insulating layer; a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and a pixel electrode connected to the drain electrode.
1. A thin film transistor array panel comprising:
a substrate;
a plurality of semiconductor regions on the substrate, wherein the respective semiconductor regions include a source region and a drain region doped with an N-type impurity, a dummy region doped with a P-type impurity, and intrinsic regions comprising a storage region and a channel region, the storage region being positioned between the drain region and the dummy region;
a gate insulating layer covering at least a portion of the semiconductor regions;
a gate line including a gate electrode and formed on the gate insulating layer, wherein the gate electrode at least partially overlaps the channel region;
a storage line including a storage electrode and formed on the gate insulating layer, wherein the storage electrode at least partially overlaps the storage region;
a data line including a source electrode connected to the source region and formed on the gate insulating layer;
a drain electrode directly contacting both the drain region and the dummy region and formed on the gate insulating layer; and
a pixel electrode connected to the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein the drain electrode at least partially overlaps the storage electrode.
3. The thin film transistor array panel of claim 1 , further comprising: a blocking layer formed between the substrate and the semiconductor regions.
4. The thin film transistor array panel of claim 1 , further comprising:
one or more lightly doped regions disposed between the source and the drain region and the channel region.