Method of wet etching vias and articles formed thereby
View Patent ↗A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead to the formation of vias that have at least one pair of opposing side walls that run parallel to a <111> plane in the wafer. A wet etchant, such as potassium hydroxide, is used to etch vias in the wafer. The use of a wet etchant leads to the formation of smooth side walls. This method allows an aspect ratio of height versus width of the vias of greater than 75 to 1.
1. A <110> silicon wafer, comprising:
a wafer substrate having opposing surfaces; and
at least one though-wafer via connecting said opposing surfaces having an aspect ratio between height and width of greater than 75 to 1 and less than 300 to 1.
2. The wafer of claim 1 , wherein the aspect ratio between height and width is between about 100 to 1 and 250 to 1.
3. The wafer of claim 1 , wherein said wafer substrate includes a primary flat surface.
4. The wafer of claim 3 , wherein said wafer substrate includes a secondary flat surface.
5. A <110> silicon wafer, comprising:
a wafer substrate having opposing surfaces; and
at least one though-wafer via connecting said opposing surfaces having an aspect ratio between height and width of greater than 75 to 1 and less than 300 to 1, wherein at least one pair of side walls of said though-wafer via run parallel to a <111> plane in the wafer.
6. The <110> silicon wafer of claim 5 , wherein the aspect ratio between height and width is between about 100 to 1 and 250 to 1.
7. The <110> silicon wafer of claim 5 , wherein said wafer substrate includes a primary flat surface.
8. The <110> silicon wafer of claim 7 , wherein said wafer substrate includes a secondary flat surface.
9. A <110> silicon wafer, comprising:
a wafer substrate; and
at least one though-wafer via having a prismatic profile and a smooth side wall, wherein an aspect ratio between a height and a width of the though-wafer via is greater than 75 to 1 and less than about 250 to 1.
10. The wafer of claim 9 , wherein at least one pair of side walls of said though-wafer via run parallel to a <111> plane in the wafer.
11. The wafer of claim 9 , wherein two pairs of side walls of said though-wafer via run parallel to a <111> plane in the wafer.
12. The wafer of claim 9 , wherein said wafer substrate includes a primary flat surface.
13. The wafer of claim 12 , wherein said wafer substrate includes a secondary flat surface.
14. A device formed from a wafer, comprising:
a substrate comprising silicon; and
at least one via extending into said substrate and having an aspect ratio between height and width of greater than 75 to 1 and less than 300 to 1, wherein at least one pair of side walls of said via run parallel to a <111> plane in the substrate.
15. The device of claim 14 , wherein the aspect ratio between height and width is between about 100 to 1 and 250 to 1.
16. The device of claim 14 , wherein the semiconductor device comprises a semiconductor chip.
17. The device of claim 14 , wherein the semiconductor device comprises a pressure sensor.
18. The device of claim 14 , wherein the semiconductor device comprises a microfluidic device.
19. A device formed from a wafer, comprising:
a substrate comprising silicon; and
at least one via having a prismatic profile and a smooth side wall, wherein at least one pair of side walls of said via run parallel to a <111> plane in the substrate, wherein an aspect ratio between a height and a width of the via is greater than 75 to 1 and less than about 250 to 1.
20. The device of claim 19 , wherein two pairs of side walls of said via run parallel to a <111> plane in the substrate.
21. The device of claim 19 , wherein the semiconductor device comprises a semiconductor chip.
22. The device of claim 19 , wherein the semiconductor device comprises a pressure sensor.
23. The device of claim 19 , wherein the semiconductor device comprises a microfluidic device.
24. A wafer, comprising:
a wafer substrate having opposing surfaces; and
at least one though-wafer via connecting said opposing surfaces having an aspect ratio between height and width of greater than 75 to 1 and less than 95 to 1.