Error checking using a field of a frame

1. A method for signal field error checking, the method comprises:

decoding a predetermined tail bit pattern of a signal field to produce a decoded tail bit pattern;

determining, for the decoded tail bit pattern, a state having a desired path metric distance;

determining whether the state having the desired path metric distance substantially corresponds to an expected state, wherein the expected state is based on the predetermined tail bit pattern; and

when the state having the desired path metric distance does not substantially correspond to the expected state, indicating a signal field error.

2. The method of claim 1 further comprises:

when the state having the desired path metric distance substantially corresponds to the expected state, indicating a valid signal field.

3. The method of claim 1 comprises, when the predetermined tail bit pattern includes a series of sequential logic zeros:

identifying one of a plurality of states of the decoding having a minimal path metric distance as the state having the desired path metric distance, wherein the expected stated corresponds to an initial state of the plurality of states.

4. The method of claim 1 comprises, when the predetermined tail bit pattern includes a series of sequential logic ones:

identifying one of a plurality of states of the decoding having a minimal path metric distance as the state having the desired path metric distance, wherein the expected stated corresponds to a state of the plurality of states having the series of sequential logic ones.

5. The method of claim 1 , wherein the decoding comprises at least one of:

Viterbi decoding;

trellis decoding; and

convolutional decoding.

6. A method for field error checking, the method comprises:

decoding a predetermined pattern of a field of a frame to produce a decoded pattern;

determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding;

comparing the path metric distance with an excepted path metric distance for the predetermined state; and

when the path metric distance compares unfavorably with the excepted path metric distance, indicating a field eror.

7. The method of claim 6 further comprises:

when the path metric distance compares unfavorably with the excepted path metric distance, indicating a valid field.

8. The method of claim 6 further comprises, when the predetermined pattern includes a series of sequential logic zeros:

utilizing an initial state of the plurality of states as the predetermined state; and

determining whether the initial state has a minimum path metric distance with respect to path metric distances of other states of the plurality of states to provide a favorable comparison of the path metric distance with the excepted path metric distance.

9. The method of claim 6 further comprises, when the predetermined pattern includes a series of sequential logic zeros:

utilizing an initial state of the plurality of states as the predetermined state;

determining whether the path metric distance is zero; and

when the path metric distance is not zero, indicating the field error.

10. The method of claim 6 further comprises, when the predetermined pattern includes a series of sequential logic ones:

utilizing a state of the plurality of states having the series of sequential logic ones as the predetermined state; and

determining whether the state of the plurality of states having the series of sequential logic ones has a minimum path metric distance with respect to path metric distances of other states of the plurality of states to provide a favorable comparison of the path metric distance with the excepted path metric distance.

11. The method of claim 6 further comprises, when the predetermined pattern includes a series of sequential logic ones:

utilizing a state of the plurality of states having the series of sequential logic ones as the predetermined state;

determining whether the path metric distance is zero; and

when the path metric distance is not zero, indicating the field error.

12. An apparatus comprises:

domain conversion module operably coupled to convert time domain signals into frequency domain symbols;

demapping module operably coupled to convert the frequency domain symbols into interleaved data;

deinterleaving module operably coupled to deinterleave the interleaved data to produce encoded data; and

a decoding module operably coupled to decode the encoded data to produce data, wherein the decoding module further functions to:

decode a predetermined tail bit pattern of a signal field to produce a decoded tail bit pattern;

determine, for the decoded tail bit pattern, a state having a desired path metric distance;

determine whether the state having the desired path metric distance substantially corresponds to an expected state, wherein the expected state is based on the predetermined tail bit pattern; and

when the state having the desired path metric distance does not substantially correspond to the expected state, indicate a signal field error.

13. The apparatus of claim 12 , wherein the decoding module further functions to:

when the state having the desired path metric distance substantially corresponds to the expected state, indicate a valid signal field.

14. The apparatus of claim 12 , wherein the decoding module further functions to, when the predetermined tail bit pattern includes a series of sequential logic zeros:

identify one of a plurality of states of the decoding having a minimal path metric distance as the state having the desired path metric distance, wherein the expected stated corresponds to an initial state of the plurality of states.

15. The apparatus of claim 12 , wherein the decoding module further functions to, when the predetermined tail bit pattern includes a series of sequential logic ones:

identify one of a plurality of states of the decoding having a minimal path metric distance as the state having the desired path metric distance, wherein the expected stated corresponds to a state of the plurality of states having the series of sequential logic ones.

16. The apparatus of claim 12 , wherein the decoding module further functions to decode the encoded data by at least one of:

Viterbi decoding;

trellis decoding; and

convolutional decoding.

17. An apparatus comprises:

domain conversion module operably coupled to convert time domain signals into frequency domain symbols;

demapping module operably coupled to convert the frequency domain symbols into interleaved data;

deinterleaving module operably coupled to deinterleave the interleaved data to produce encoded data; and

a decoding module operably coupled to decode the encoded data to produce data, wherein the decoding module further functions to:

decode a predetermined pattern of a field of a frame to produce a decoded pattern;

determine, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding;

compare the path metric distance with an excepted path metric distance for the predetermined state; and

when the path metric distance compares unfavorably with the excepted path metric distance, indicate a field error.

18. The apparatus of claim 17 , wherein the decoding module further functions to:

when the path metric distance compares unfavorably with the excepted path metric distance, indicate a valid field.

19. The apparatus of claim 17 , wherein the decoding module further functions to, when the predetermined pattern includes a series of sequential logic zeros:

utilize an initial state of the plurality of states as the predetermined state; and

determine whether the initial state has a minimum path metric distance with respect to path metric distances of other states of the plurality of states to provide a favorable comparison of the path metric distance with the excepted path metric distance.

20. The apparatus of claim 17 , wherein the decoding module further functions to, when the predetermined pattern includes a series of sequential logic zeros:

utilize an initial state of the plurality of states as the predetermined state;

determine whether the path metric distance is zero; and

when the path metric distance is not zero, indicate the field error.

21. The apparatus of claim 17 , wherein the decoding module further functions to, when the predetermined pattern includes a series of sequential logic ones:

utilize a state of the plurality of states having the series of sequential logic ones as the predetermined state; and

determine whether the state of the plurality of states having the series of sequential logic ones has a minimum path metric distance with respect to path metric distances of other states of the plurality of states to provide a favorable comparison of the path metric distance with the excepted path metric distance.

22. The apparatus of claim 17 , wherein the decoding module further functions to, when the predetermined pattern includes a series of sequential logic ones:

utilize a state of the plurality of states having the series of sequential logic ones as the predetermined state;

determine whether the path metric distance is zero; and

when the path metric distance is not zero, indicate the field error.