Procedure and circuit device for the subtraction of electrical signals
View Patent ↗The invention relates to a procedure and a circuit device for the subtraction of electrical signals, with at least two regulating loops each comprising at least one amplifier unit. Advantageously, the circuit device comprises a device for subtracting a signal, made available by the circuit device and representing the difference between the electrical signals, from one of the electrical signals. In a preferred embodiment of the invention, the potentials on lines carrying the electrical signals are maintained at the same value with the help of a first one or of the regulating loops.
1. A circuit for the subtraction of input electrical signals, the circuit comprising:
regulating loops, wherein each regulating loop comprises at least one amplifier unit;
a subtraction device for subtracting a derived signal representing the difference between the input electrical signals, from one of the input electrical signals, said derived signal made available by the circuit; and
a mirroring device for mirroring the derived signal and representing the difference between the input electrical signals.
2. The circuit according to claim 1 , in which potentials on lines carrying the electrical signals are maintained at a same value with help of a first one of the regulating loops.
3. The circuit according to claim 1 , further comprising transistors in the signal path of the circuit, wherein the transistors provided in the signal path of the circuit device are a same type.
4. The circuit according to claim 3 , wherein the transistors provided in the signal path of the circuit device are NMOS field effect transistors.
5. The circuit according to claim 3 , wherein the transistors provided in the signal path of the circuit device are PMOS field effect transistors.
6. A procedure for the subtraction of input electrical signals, comprising:
providing at least two regulating loops, a first one of said regulating loops comprising at least one amplifier unit, and a second one of said regulating loops comprising at least one amplifier unit that is a different amplifier unit than the amplifier unit of said first regulating loop;
maintaining potentials on lines carrying the electrical signals at a same value; and
mirroring a derived signal representing the difference between the input electrical signals.
7. The procedure according to claim 6 , further comprising subtracting a signal, representing a difference between the electrical signals, from one of the electrical signals.
8. The circuit device according to claim 3 , further comprising additional subtracting devices for subtracting other electrical signals made available by the circuit device and representing the difference between the other electrical signals, from one of the electrical signals.
9. A circuit for the subtraction of input electrical signals, the circuit comprising:
regulating loops, wherein each regulating loop comprises at least one amplifier unit;
transistors in a signal path of the circuit device, wherein the transistors provided in the signal path of the circuit are a same type; and
a mirroring device for mirroring a signal made available by the circuit and representing a difference between the input electrical signals.
10. The circuit according to claim 9 , wherein the transistors provided in the signal path of the circuit device are NMOS field effect transistors.
11. The circuit according to claim 9 , wherein the transistors provided in the signal path of the circuit device are PMOS field effect transistors.
12. The circuit device according to claim 9 , further comprising additional subtracting devices for subtracting other electrical signals made available by the circuit device and representing the difference between the other electrical signals, from one of the electrical signals.
13. A circuit for the subtraction of input electrical signals, the circuit comprising:
at least a first regulating loop and a second regulating loop, wherein said first regulating loop comprises a first amplifier unit and said second regulating loop comprises a second amplifier unit different than said amplifier unit of said first regulating loop; and
a subtraction device for subtracting a derived signal representing the difference between the input electrical signals, from one of the input electrical signals, said derived signal made available by the circuit.
14. The circuit according to claim 13 , further comprising a mirroring device for mirroring the signal made available by the circuit device and representing the difference between the electrical signals.
15. The circuit according to claim 13 , in which potentials on lines carrying the electrical signals are maintained at a same value with help of a first one of the regulating loops.
16. The circuit according to claim 13 , further comprising transistors in the signal path of the circuit wherein the transistors provided in the signal path of the circuit are a same type.
17. The circuit according to claim 13 , wherein the transistors provided in the signal path of the circuit device are NMOS field effect transistors.
18. The circuit according to claim 13 , wherein the transistors provided in the signal path of the circuit device are PMOS field effect transistors.
19. A circuit for the subtraction of input electrical signals carried on a first input line and a second input line, the circuit comprising:
a current mirror connected to the first input line and the second input line for subtracting a derived signal representing the difference between the input electrical signals from one of the input electrical signals; and
at least one regulating loop for maintaining potentials on the input lines at a same value.