Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor
View Patent ↗A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.
1. A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, comprising:
orthogonal wires formed on a standard grid which has a pitch P and extends in a horizontal or vertical direction, and disposed at intervals of at least said pitch P; and
diagonal wires inclined by 45° or 135° in relation to said orthogonal wires,
wherein said diagonal wires include a first diagonal wire formed on a grid point of said standard grid and a second diagonal wire formed on a ½ grid point at which said standard grid intersects a ½ grid which is displaced from said standard grid by P/2, said first and second diagonal wires being disposed at intervals of at least (1.5/√{square root over (2)})×P in relation to said pitch P.
2. The semiconductor integrated circuit device according to claim 1 , wherein said orthogonal wires are formed on said ½ grid in addition to said standard grid.
3. The semiconductor integrated circuit device according to claim 1 , wherein the minimum wire width of said diagonal wire is substantially same as the minimum wire width of said orthogonal wire.
4. The semiconductor integrated circuit device according to claim 1 , wherein the positions on said orthogonal wire at which the orthogonal wire intersects said first and second diagonal wires have a minimum pitch of 1.5P.
5. The semiconductor integrated circuit device according to claim 1 , wherein an orthogonal wire which is adjacent to a predetermined orthogonal wire intersects a diagonal wire which is adjacent to a predetermined diagonal wire at a position which is located a knight's move from the intersection position of said predetermined orthogonal wire and said predetermined diagonal wire.
6. A semiconductor integrated circuit wiring layout program for causing a computer to execute a wiring layout procedure for a semiconductor integrated circuit having a plurality of circuit elements and a plurality of wires connecting the circuit elements, said wiring layout procedure comprising:
generating data, in a first wiring layer, for orthogonal wires disposed on a standard grid, which has a pitch P and extends in a horizontal or vertical direction, at intervals of at least said pitch P; and
generating data, in a second wiring layer, which differs from said first wiring layer, for diagonal wires inclined by 45° or 135° in relation to said orthogonal wires, said data for diagonal wires including data for a first diagonal wire formed on a grid point of said standard grid, and data for a second diagonal wire formed on a ½ grid point at which said standard grid intersects a ½ grid which is displaced from said standard grid by P/2,
wherein said first and second diagonal wires are disposed at intervals of at least (1.5/√{square root over (2)})×P in relation to said pitch P.