Computer system
View Patent ↗A technology for allowing the smooth acquisition of required data when a processor switches working modes in a computer system is provided. According to one aspect of the present invention, the present invention can provide a computer system including a processor having a plurality of working modes, each having a different privilege level from each other; an exclusive memory area related to a selected one of said plurality of working modes; and a connecting means for connecting said processor with said exclusive memory, depending on said working mode.
1. A computer system comprising:
a processor comprising a first working mode, and a second working mode having a different privilege level from said first working mode;
a first instruction cache memory area configurable to store program instructions read from main memory and that is accessed by said processor during said first working mode, where the instructions stored in the first instruction cache are the same as instructions stored in the main memory;
a second instruction cache memory area configurable to store program instructions read from main memory and that is accessed by said processor during said second working mode, where the instructions stored in the second instruction cache are the same as instructions in the main memory; and
circuitry configurable to respond to a current working mode to automatically select one of said first instruction cache memory area or said second instruction cache memory area to provide program instructions to be executed by said processor.
2. A computer system according to claim 1 , comprising circuitry for changing a size of said first instruction cache and second instruction cache memory areas.
3. A computer system according to claim 1 , comprising circuitry for changing a size of said first instruction and second instruction cache memory areas autonomously.
4. A computer system according to claim 1 , wherein at least one of said first instruction cache or second instruction cache memory areas is comprised of SRAM.
5. A computer system according to claim 1 , wherein:
data imported from outside is stored in said first instruction cache memory area when said processor is in said first working mode, and data imported from outside is stored in said second instruction cache memory area when said processor is in said second working mode.
6. A computer system according to claim 1 , wherein said first instruction cache memory area and said instruction cache second memory area separately exist on physically different storage media.
7. A computer system according to claim 1 , wherein said first instruction cache memory area and said second instruction cache memory area exist in different logical partitions on the same storage medium.
8. A computer system according to claim 7 , wherein said circuitry is responsive to an address generated by said processor to connect said processor to an associated one of the logical sections of the first instruction cache memory area or the second instruction cache memory area.
9. A computer system according to claim 1 , wherein the computer system is integrated into a single-chip LSI.
10. A computer system according to claim 1 , wherein the computer system is a mobile electronics device.
11. A computer program, collaborating with the computer system according to claim 1 and comprising instructions to instruct said processor of changes in the number or size of said first instruction cache or said second instruction cache memory areas.
12. A method, comprising:
operating a data processor in a first working mode by reading program instructions from a first instruction cache, where the instructions read from the first instruction cache are the same as instructions stored in main memory;
switching the data processor to a second working mode having a lower privilege level than the first working mode; and
operating the data processor in the second working mode by reading program instructions from a second instruction cache, where the instructions read from the second instruction cache are the same as instructions stored in the main memory; where
the steps of operating include automatically selecting, based at least on memory addresses generated by the data processor, either the first instruction cache or the second instruction cache to provide program instructions to be executed by the data processor.
13. The method of claim 12 , where the first instruction cache is embodied in a first memory medium, and where the second instruction cache is embodied in a second memory medium.
14. The method of claim 12 , where the first instruction cache and the second instruction cache are embodied in a single memory medium.
15. The method of claim 12 , where at least the first instruction cache is operated as a set-associate instruction cache.
16. The method of claim 12 , executed within an integrated circuit that comprises said data processor and said first and second instruction caches.
17. The method of claim 12 , executed within a mobile electronics device.
18. The method of claim 12 , where the first instruction cache is an exclusive memory area for the first working mode and the second instruction cache is an exclusive memory area for the second working mode.
19. An integrated circuit, comprising:
a first memory configurable to store a first instruction cache;
a second memory configurable to store a second instruction cache;
a data processor configurable to operate in a first working mode by reading program instructions from the first instruction cache, where the instructions read from the first instruction cache are the same as instructions stored in main memory, and to operate in a second working mode by reading program instructions from the second instruction cache, where the instructions read from the second instruction cache are the same as instructions in the main memory, where the first working mode operates with a higher privilege level than the second working mode; and
circuitry configurable to select, based at least on memory addresses generated by said data processor, either the first memory or the second memory to provide program instructions to be executed by said data processor.
20. The integrated circuit of claim 19 , where the first memory and the second memory comprise two physically distinct memory medium.
21. The integrated circuit of claim 19 , where the first memory and the second memory comprise a single memory medium.
22. The integrated circuit of claim 19 , where at least the first instruction cache is operated as a set-associate instruction cache.
23. The integrated circuit of claim 19 , embodied within a mobile electronics device.
24. The integrated circuit of claim 19 , where the first instruction cache is an exclusive memory for the first working mode and the second instruction cache is an exclusive memory for the second working mode.