Method and apparatus for spreading and modulating communication signals
View Patent ↗According to one embodiment, a lower order modulator is provided using a number of higher order modulators. According to another embodiment, a signal having a lower order spreading factor is generated using circuitry for generating a number of signals with a higher order spreading factor.
1. A bi-phased shift keying (BPSK) modulator, comprising:
a first mapper configured to generate a first set of inputs based on a first and a second input bit;
a second mapper configured to generate a second set of inputs based on a third and a fourth input bit;
a first QPSK modulator generating a first QPSK signal based on the first set of inputs;
a second QPSK modulator generating a second QPSK signal based on the second set of inputs; and
a combiner combining the first and second QPSK signals to generate a BPSK signal.
2. The BPSK modulator of claim 1 , wherein
the first QPSK modulator performs a first spreading operation according to a first spreading factor;
the second QPSK modulator performs a second spreading operation according to the first spreading factor; and
the first mapper generates the first set of inputs and the second mapper generates the second set of inputs such that the BPSK signal has a second spreading factor, which is less than the first spreading factor.
3. The BPSK modulator of claim 2 , wherein the first spreading factor is 4 and the second spreading factor is 2.
4. The BPSK modulator of claim 3 , wherein
the first QPSK modulator performs the first spreading operation using a first spreading pattern of 1 ,− 1 , 1 ,− 1 ;
the second QPSK modulator performs the second spreading operation using a second spreading pattern of 1 ,− 1 ,− 1 , 1 ; and
the BPSK signal has a spreading pattern of 1 ,− 1 .
5. The BPSK modulator of claim 1 , wherein the first set of inputs are first I and Q signals; and the second set of inputs are second I and Q signals.
6. The BPSK modulator of claim 5 , wherein
the first mapper maps the first input bit and the second input bit into the first I and Q signals based on a first control signal and a second control signal;
the second mapper maps the third input bit and the fourth input bit into the second I and Q signals based on a third control signal and a fourth control signal;
the first mapper includes a first logic unit generating the first input bit, the second input bit, the first control signal and the second control signal based on received first and second bits; and
the second mapper includes a second logic unit generating the third input bit, the fourth input bit, the third control signal and the fourth control signal based on the received first and second bits.
7. The BPSK modulator of claim 6 , wherein
the first and second control signals are a first I DTX control signal and a first Q DTX control signal, respectively; and
the third and fourth control signals are a second I DTX control signal and a second Q DTX control signal, respectively.
8. The BPSK modulator of claim 7 , wherein
the first logic unit generates a zero as the first input bit, an AND of the received first and second bits as the second input bit, a zero as the first I DTX signal, and an inverse of an exclusive OR of the received first and second bits as the first Q DTX signal; and
the second logic unit generates a zero as the third input bit; an AND of the received first bit and an inverse of the received second bit as the fourth input bit, a zero as the second I DTX signal, and an exclusive OR of the received first and second bits as the second Q DTX signal.
9. The BPSK modulator of claim 8 , wherein
the first QPSK modulator performs a first spreading operation on the first I and Q signals using a first spreading pattern 1 ,− 1 , 1 ,− 1 ; and
the second QPSK modulator performs a second spreading operation on the second I and Q signals using a second spreading pattern of 1 ,− 1 ,− 1 , 1 .
10. The BPSK modulator of claim 1 , wherein
the first and second input bits are a first I DTX control signal and a first Q DTX control signal, respectively; and
the third and fourth input bits are a second I DTX control signal and a second Q DTX control signal, respectively.
11. The BPSK modulator of claim 10 , wherein
the first mapper includes a first logic unit generating a zero as the first input bit, an AND of the received first and second bits as the second input bit, a zero as the first I DTX signal, and an inverse of an exclusive OR of the received first and second bits as the first Q DTX signal; and
the second mapper includes a second logic unit generating a zero as the third input bit; an AND of the received first bit and an inverse of the received second bit as the fourth input bit, a zero as the second I DTX signal, and an exclusive OR of the received first and second bits as the second Q DTX signal.
12. The BPSK modulator of claim 11 , wherein
the first QPSK modulator performs a first spreading operation on the first I and Q signals using a first spreading pattern of 1 ,− 1 , 1 ,− 1 ; and
the second QPSK modulator performs a second spreading operation on the second I and Q signals using a second spreading pattern of 1 ,− 1 ,− 1 , 1 .