Latency circuit for semiconductor memories
A random access memory includes an array of memory cells, a mode register and a controller. The mode register is configured to hold a programmable minimum timing requirement. The controller is configured to retrieve the programmable minimum timing requirement and to access the array of memory cells in a double data rate prefetch mode in response to a read command after the programmable minimum timing requirement is met.
1 . A random access memory comprising:
an array of memory cells;
a mode register configured to hold a programmable minimum timing requirement; and
a controller configured to retrieve the programmable minimum timing requirement and to access the array of memory cells in a double data rate prefetch mode in response to a read command after the programmable minimum timing requirement is met.
2 . The random access memory of claim 1 , wherein the programmable minimum timing requirement is a minimum time between a row address strobe and a column address strobe.
3 . The random access memory of claim 2 , wherein the minimum time between a row address strobe and a column address strobe is calculated as a number of clock cycles and stored into the mode register.
4 . The random access memory of claim 3 , wherein the controller is configured to determine the number of clock cycles based upon the frequency of a system clock and characteristics of the random access memory
5 . A random access memory comprising:
an array of memory cells;
a signal generating circuit within the random access memory for generating a programmable minimum timing signal; and
a controller configured to be responsive to the retrieve the programmable minimum timing signal and to access the array of memory cells in a double data rate prefetch mode in response to a read command after the programmable minimum timing signal transitions states indicating that a minimum time parameter has been met.
6 . The random access memory of claim 5 , wherein the signal generating circuit further comprises a counter configured to track clock cycles after a row address strobe and output a signal indicative of number of clock cycles.
7 . The random access memory of claim 6 , wherein the signal generating circuit further comprises a mode register configured to store a minimum time between a row address strobe and a column address strobe and a column address strobe and generate an output signal indicative of the minimum time.
8 . The random access memory of claim 7 , wherein the signal generating circuit further comprises a comparator configured to compare the output of the counter with the output of the mode register in order to generate a signal indicative of when the minimum time has been met.
9 . The random access memory of claim 8 , wherein the minimum time stored in the mode register is a tRCD signal.
10 . A random access memory comprising:
an array of memory cells;
means within the random access memory for storing a programmable time component representative of a number of clock cycles between a row address strobe and a column address strobe; and
a controller configured to retrieve the programmable time component and to access the array of memory cells in a double data rate prefetch mode in response to a read command after the programmable time component is met.
11 . The random access memory of claim 10 , wherein the programmable time component is stored outside the controller so that the controller does not have to calculate or store the programmable minimum timing requirement.
12 . The random access memory of claim 10 , wherein the programmable time component allows the controller to issue back-to-back read commands without using additive latency and without causing gaps in data read out of the memory cells.
13 . A method of accessing a random access memory comprising:
storing a timing parameter representative of a minimum time required between a row address strobe and a column address strobe for the random access memory;
receiving an active command;
initiating counting in accordance with the timing parameter; and
accessing the array of memory cells in a double data rate prefetch mode in response to a read command after the counting in accordance with the timing parameter indicates that the minimum time required between a row address strobe and a column address strobe for the random access memory is met.
14 . The method of claim 13 , further including calculating the minimum time between a row address strobe and a column address strobe as a number of clock cycles and storing the number of clock cycles into a mode register.
15 . The method of claim 14 , further including determining the number of clock cycles based upon the frequency of a system clock and characteristics of the random access memory
16 . A method for accessing a memory, the method comprising:
generating a programmable minimum timing signal; and
accessing an array of memory cells within the memory in a double data rate prefetch mode in response to a read command after the programmable minimum timing signal transitions states thereby indicating that a minimum time parameter has been met.
17 . The method of claim 16 , further including using tracking clock cycles after a row address strobe and outputting a signal indicative of number of clock cycles.
18 . The method of claim 17 , further including storing a minimum time between a row address strobe and a column address strobe and a column address strobe and generating an output signal indicative of the minimum time.
19 . The random access memory of claim 18 , further including comparing the signal indicative of number of clock cycles with the signal indicative of the minimum time in order to generate a signal indicative of when the minimum time has been met.
20 . The random access memory of claim 19 , wherein the minimum time stored is a tRCD signal.