IP Library Granted Patent US 7,571,368
Granted Patent B1
US 7,571,368 · App. 11/340,099 · Granted Aug 4, 2009

Digital content protection systems and methods

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Quick Facts
Patent No.
US 7,571,368
App. No.
11/340,099
Granted
Aug 4, 2009
Kind
B1
Abstract

In an embodiment of the invention, an integrated circuit comprises an input module configured to receive a first data segment, an identifier module having a hard coded identifier, a processing module coupled to the input module and coupled to the identifier module and configured to process the first data segment with the hard coded identifier to generate a first error correction code, and an output module configured to transfer the first error correction code for storage on a storage system.

Claims (31)

1. An integrated circuit comprising:

an input module configured to receive a first data segment;

an identifier module having a hard coded identifier;

a processing module coupled to the input module and coupled to the identifier module and configured to process the first data segment with the hard coded identifier to generate a first error correction code;

an output module configured to transfer the first error correction code for storage on a storage system;

wherein the input module is further configured to receive a second data segment and a second error correction code; and

wherein the processing module is further configured to process the second data segment with the second error correction code to generate a first result, process the first result with the hard coded identifier to generate a second result, and process the second data segment with the second result to correct the second data segment.

2. The integrated circuit of claim 1 wherein the identifier module comprises a plurality of inputs connected to the processing module wherein the hard coded identifier is identified by setting the plurality of inputs during a manufacturing process.

3. The integrated circuit of claim 2 wherein the plurality of inputs comprise a plurality of pins.

4. The integrated circuit of claim 2 wherein the plurality of inputs comprise a plurality of fuses.

5. The integrated circuit of claim 2 wherein the plurality of inputs comprise a plurality of electrical inputs.

6. The integrated circuit of claim 5 wherein the plurality of inputs comprise a plurality of current inputs.

7. The integrated circuit of claim 5 wherein the plurality of inputs comprise a plurality of voltage inputs.

8. A method of operating an integrated circuit comprising an input module, an output module, and a processing module coupled to the input module and the output module, the method comprising:

in the input module, receiving a first data segment;

in the processing module, reading a hard coded identifier from an identifier module coupled to the processing module, processing the first data segment with the hard coded identifier to generate a first error correction code;

in the output module, transferring the first error correction code for storage on a storage system;

in the input module, receiving a second data segment and a second error correction code; and

in the processing module, processing the second data segment with the second error correction code to generate a first result, processing the first result with the hard coded identifier to generate a second result, and processing the second data segment with the second result to correct the second data segment.

9. The method of claim 8 wherein the identifier module comprises a plurality of inputs connected to the processing module wherein the hard coded identifier is identified by setting the plurality of inputs during a manufacturing process.

10. The method of claim 9 wherein the plurality of inputs comprise a plurality of pins.

11. The method of claim 9 wherein the plurality of inputs comprise a plurality of fuses.

12. The integrated circuit of claim 9 wherein the plurality of inputs comprise a plurality of electrical inputs.

13. The integrated circuit of claim 12 wherein the plurality of inputs comprise a plurality of current inputs.

14. The integrated circuit of claim 12 wherein the plurality of inputs comprise a plurality of voltage inputs.

15. A device comprising:

a storage medium; and

a host system having a plurality of system elements and a storage control system for controlling data transfer between the plurality of system elements and the storage medium, the storage control system comprising:

a content protection system configured to receive a first data segment from a one of the plurality of system elements, read a hard coded identifier, process the first data segment with the hard coded identifier to generate a first error correction code, and transfer the first error correction code for storage on the storage medium; and

a transfer system configured to transfer the first data segment with the first error correction code to the storage medium; and

wherein the content protection system is further configured to receive a second data segment and a second error correction code, process the second data segment with the second error correction code to generate a first result, process the first result with the hard coded identifier to generate a second result, and process the second data segment with the second result to correct the second data segment.

Assignments (6)
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040821/0550 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2010
From: PROMETHEAN STORAGE LLC
To: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
Reel/Frame 025353/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2006
From: BRUNER, CURTIS H.; SQUIRES, CHRISTOPHER J.; REH, JEFFREY G.
To: PROMETHEAN STORAGE LLC
Reel/Frame 017506/0734 →